# US 2021/0240345 A1 · Nonvolatile semiconductor memory device

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- Number: US 2021/0240345 A1
- Document ID: US20210240345A1
- Status: Published application
- Kind: A1
- Application number: 17/238,822
- Filed: 2021-04-23
- Published: 2021-08-05
- Earliest claimed: 2009-04-14
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Takuya FUTATSUYAMA
- Web page: https://patentgrep.com/patent/US20210240345A1

## CPC

- G06F 3/061: {Improving I/O performance}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0652: {Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/045: {Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

## Claims

### Claim 1

(canceled)

### Claim 2

A method for controlling a nonvolatile semiconductor memory device,
the nonvolatile semiconductor memory device comprising:
a memory cell array including:
a first selection gate transistor,
a second selection gate transistor, and
a plurality of serially-connected memory cells provided between the first selection gate transistor and the second selection gate transistor,
the memory cells including:
a first memory cell connected with a first word line and capable of being programmed in one stage and storing data of one bit,
a second memory cell connected with a second word line and capable of being programmed in multi stages and storing data of three bits, the second memory cell being closer to the first selection gate transistor as compared with the first memory cell,
a third memory cell connected with a third word line and capable of being programmed in the multi stages and storing data of three bits, the third memory cell being closer to the first selection gate transistor as compared with the second memory cell, and
a fourth memory cell connected with a fourth word line and capable of being programmed in the multi stages and storing data of three bits, the fourth memory cell being closer to the first selection gate transistor as compared with the third memory cell,
the method comprising:
performing a first program on the third memory cell as a non-final stage of the multi stages;
performing a second program on the fourth memory cell as a final stage of the multi stages, after performing the first program;
performing a third program on the second memory cell as the non-final stage of the multi stages, after performing the second program;
performing a fourth program on the third memory cell as the final stage of the multi stages, after performing the third program;
performing a fifth program on the first memory cell as the non-final stage of the multi stages, after performing the fourth program; and
performing a sixth program on the second memory cell as the final stage of the multi stages, after performing the fifth program.

### Claim 3 (depends on 2)

The method according to claim 2, wherein
the memory cells further include:
a fifth memory cell connected with a fifth word line and capable of being programmed in the multi stages and storing data of three bits, the fifth memory cell being closer to the first selection gate transistor as compared with the fourth memory cell,
the method further comprising:
performing a seventh program on the fifth memory cell as the final stage of the multi stages, before performing the first program; and
performing an eighth program on the fourth memory cell as the non-final stage of the multi stages, before performing the seventh program.

### Claim 4 (depends on 3)

The method according to claim 3, wherein
the multi stages includes a first stage, a second stage, and a third stage, and
the non-final stage is the second stage, and the final stage is the third stage.

### Claim 5 (depends on 4)

The method according to claim 4, further comprising:
performing a ninth program on the third memory cell as the first stage of the multi stages, before performing the eighth program; and
performing a tenth program on the second memory cell as the first stage of the multi stages, after performing the seventh program and before performing the first program.

### Claim 6 (depends on 2)

The method according to claim 2, wherein
the memory cell array further includes:
a first dummy cell having a structure same as one of the memory cells between the second selection gate transistor and the first memory cell, and
a second dummy cell having a structure same as one of the memory cells between the first selection gate transistor and the fourth memory cell.

### Claim 7 (depends on 2)

The method according to claim 2, wherein
the nonvolatile semiconductor memory device further includes:
a source line connected to a source of the first selection gate transistor, and
a bit line connected to a drain of the second selection gate transistor.

### Claim 8

A method for controlling a nonvolatile semiconductor memory device,
the nonvolatile semiconductor memory device comprising:
a memory cell array including:
a first selection gate transistor,
a second selection gate transistor, and
a plurality of serially-connected memory cells provided between the first selection gate transistor and the second selection gate transistor,
the memory cells including:
a first memory cell connected with a first word line and capable of being storing data of two bits,
a second memory cell connected with a second word line and capable of storing data of three bits, the second memory cell being closer to the first selection gate transistor as compared with the first memory cell,
a third memory cell connected with a third word line and capable of storing data of three bits, the third memory cell being closer to the first selection gate transistor as compared with the second memory cell,
a fourth memory cell connected with a fourth word line and capable of storing data of three bits, the fourth memory cell being closer to the first selection gate transistor as compared with the third memory cell, and
a fifth memory cell connected with a fifth word line and capable of storing data of three bits, the fifth memory cell being closer to the first selection gate transistor as compared with the fourth memory cell,
the method comprising:
performing a first program on the fourth memory cell as a non-final one of stages for writing three bits;
performing a second program on the fifth memory cell as a final one of stages for writing three bits, after performing the first program;
performing a third program on the third memory cell as the non-final one of stages for writing three bits, after performing the second program;
performing a fourth program on the fourth memory cell as the final one of stages for writing three bits, after performing the third program;
performing a fifth program on the second memory cell as the non-final one of stages for writing three bits, after performing the fourth program;
performing a sixth program on the first memory cell as a final one of stages for writing two bits, after performing the fifth program; and
performing a seventh program on the second memory cell as the final one of stages for writing three bits, after performing the sixth program.

### Claim 9 (depends on 8)

The method according to claim 8, further comprising:
performing an eighth program on the first memory cell as a non-final one of stages for writing two bits, after performing the fourth program and before performing the fifth program.

### Claim 10 (depends on 9)

The method according to claim 9, wherein
the three bits are written in first to third stages, among which the third stage corresponds to the final one of stages, and the second stage corresponds to the non-final one of stages, and
the two bits are written in first and second stages, among which the second stage corresponds to the final one of stages, and the first stage corresponds to the non-final one of stages.

### Claim 11 (depends on 10)

The method according to claim 10, further comprising:
performing a ninth program on the third memory cell as the first stage for writing three bits, before performing the first program; and
performing a tenth program on the second memory cell as the first stage for writing three bits, after performing the second program before performing the third program.

### Claim 12 (depends on 8)

The method according to claim 8, wherein
the memory cell array further includes:
a first dummy cell having a structure same as one of the memory cells between the second selection gate transistor and the first memory cell, and
a second dummy cell having a structure same as one of the memory cells between the first selection gate transistor and the fifth memory cell.

### Claim 13 (depends on 8)

The method according to claim 8, wherein
the nonvolatile semiconductor memory device further includes:
a source line connected to a source of the first selection gate transistor, and
a bit line connected to a drain of the second selection gate transistor.

### Claim 14

A method for controlling a nonvolatile semiconductor memory device,
the nonvolatile semiconductor memory device comprising:
a memory cell array including:
a first selection gate transistor,
a second selection gate transistor, and
a plurality of serially-connected memory cells provided between the first selection gate transistor and the second selection gate transistor,
the memory cells including:
a first memory cell connected with a first word line and capable of being programmable in D1 stages to thereby store data of D1 bits, D1 being an integer of 1 or more,
a second memory cell connected with a second word line and capable of being programmable in D2 stages to thereby store data of D2 bits, D2 being an integer of 3 or more and greater than D1, the second memory cell being closer to the first selection gate transistor than the first memory cell,
a third memory cell connected with a third word line and capable of being programmable in D3 stages to thereby store data of D3 bits, D3 being an integer of 3 or more and greater than D1, the third memory cell being closer to the first selection gate transistor than the second memory cell, and
a fourth memory cell connected with a fourth word line and capable of being programmable in D4 stages to thereby store data of D4 bits, D4 being an integer of 3 or more and greater than D1, the fourth memory cell being closer to the first selection gate transistor than the third memory cell,
the method comprising:
performing a first program on the third memory cell as a first one of the D3 stages;
performing a second program on the fourth memory cell as a second or higher one of the D4 stages, after performing the first program;
performing a third program on the second memory cell as a first one of the D2 stages, after performing the second program,
performing a fourth program on the third memory cell as a second or higher one of the D3 stages, after performing the third program;
performing a fifth program on the first memory cell as a first one of the D1 stages, after performing the fourth program; and
performing a sixth program on the second memory cell as a second or higher one of the D2 stages, after performing the fifth program.

### Claim 15 (depends on 14)

The method according to claim 14, wherein
the sixth program on the second memory cell is performed as the second one of the D2 stages, and
the method further comprises:
performing a seventh program on the second memory cell as a third or higher one of the D2 stages, after performing the sixth program.

### Claim 16 (depends on 15)

The method according to claim 15, wherein
the second program on the fourth memory cell is performed as the second one of the D4 stages,
the fourth program on the third memory cell is performed as the second one of the D3 stages, and
the method further comprises:
performing an eighth program on the fourth memory cell as a third or higher one of the D4 stages, after performing the third program and before performing the fifth program, and
performing a ninth program on the third memory cell as a third or higher one of the D3 stages, after performing the fifth program and before performing the seventh program.

### Claim 17 (depends on 14)

The method according to claim 14, wherein
D1 is 1,
D2 is 3,
D3 is 3, and
D4 is 3.

### Claim 18 (depends on 14)

The method according to claim 14, wherein
the memory cell array further includes:
a first dummy cell having a structure same as one of the memory cells between the second selection gate transistor and the first memory cell, and
a second dummy cell having a structure same as one of the memory cells between the first selection gate transistor and the fourth memory cell.

### Claim 19 (depends on 14)

The method according to claim 14, wherein
the nonvolatile semiconductor memory device further includes:
a source line connected to a source of the first selection gate transistor, and
a bit line connected to a drain of the second selection gate transistor.

### Claim 20

A method for controlling a nonvolatile semiconductor memory device, comprising:
a memory cell array including:
a first selection gate transistor,
a second selection gate transistor, and
a plurality of serially-connected memory cells provided between the first selection gate transistor and the second selection gate transistor,
the memory cells including:
a first memory cell connected with a first word line and capable of being programmable in D1 stages to thereby store data of D1 bits, D1 being an integer of 1 or more,
a second memory cell connected with a second word line and capable of being programmable in D2 stages to thereby store data of D2 bits, D2 being an integer of 3 or more and greater than D1, the second memory cell being closer to the first selection gate transistor than the first memory cell,
a third memory cell connected with a third word line and capable of being programmable in D3 stages to thereby store data of D3 bits, D3 being an integer of 3 or more and greater than D1, the third memory cell being closer to the first selection gate transistor than the second memory cell, and
a fourth memory cell connected with a fourth word line and capable of being programmable in D4 stages to thereby store data of D4 bits, D4 being an integer of 3 or more and greater than D1, the fourth memory cell being closer to the first selection gate transistor than the third memory cell,
the method comprising:
performing a first program on the third memory cell as a second or lower one of the D3 stages;
performing a second program on the fourth memory cell as a final one of the D4 stages, after performing the first program;
performing a third program on the second memory cell as a second or lower one of the D2 stages, after performing the second program;
performing a fourth program on the third memory cell as a final one of the D3 stages, after performing the third program;
performing a fifth program on the first memory cell as a first or higher one of the D1 stages, after performing the fourth program; and
performing a sixth program on the second memory cell as a final one of the D2 stages, after performing the fifth program.

### Claim 21 (depends on 20)

The method according to claim 20, wherein
the third program on the second memory cell is performed as the second one of the D2 stages, and
the method further comprises:
performing a seventh program on the second memory cell as a first one of the D2 stages, before performing the first program.

### Claim 22 (depends on 21)

The method according to claim 21, wherein
the first program on the third memory cell is performed as the second one of the D3 stages, and
the method further comprises:
performing an eighth program on the third memory cell as a first one of the D4 stages, before performing the seventh program.

### Claim 23 (depends on 20)

The method according to claim 20, wherein
D1 is 1,
D2 is 3,
D3 is 3, and
D4 is 3.

### Claim 24 (depends on 20)

The method according to claim 20, wherein
the memory cell array further includes:
a first dummy cell having a structure same as one of the memory cells between the second selection gate transistor and the first memory cell, and
a second dummy cell having a structure same as one of the memory cells between the first selection gate transistor and the fourth memory cell.

### Claim 25 (depends on 20)

The method according to claim 20, wherein
the nonvolatile semiconductor memory device further includes:
a source line connected to a source of the first selection gate transistor, and
a bit line connected to a drain of the second selection gate transistor.