# US 2021/0240344 A1 · Wafer-scale memory techniques

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- Number: US 2021/0240344 A1
- Document ID: US20210240344A1
- Status: Published application
- Kind: A1
- Application number: 17/162,796
- Filed: 2021-01-29
- Published: 2021-08-05
- Earliest claimed: 2020-02-03
- Assignees: Micron Technology, Inc.
- Inventors: Brent Keeth; Bambi L. DeLaRosa; Eiichi Nakano
- Web page: https://patentgrep.com/patent/US20210240344A1

## CPC

- H10W 90/00: Package configurations
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 80/00: Direct bonding of chips, wafers or substrates
- G06F 3/061: {Improving I/O performance}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]}
- G11C 2029/1206: {Location of test circuitry on chip or wafer}
- G11C 2207/105: Aspects related to pads, pins or terminals
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm2).

## Claims

### Claim 1

A wafer-scale memory device comprising:
a single substrate having a memory area across a major surface area of more than 20,000 square millimeters (mm2);
the memory area formed by multiple memory circuit areas, the multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate; and
multiple streets separating respective memory circuit areas, the streets configured to provide attachment locations for attaching the substrate to a wafer-scale processor.

### Claim 2 (depends on 1)

The wafer-scale memory device of claim 1, wherein each memory circuit area includes multiple tiled memory circuits.

### Claim 3 (depends on 2)

The wafer-scale memory device of claim 2, wherein each memory tile circuit includes terminations of 128 channels of the DRAM memory, the terminations configured to couple with terminations of the wafer-scale processor.

### Claim 4 (depends on 3)

The wafer-scale memory device of claim 3, wherein the terminations are arranged in 16 input/output (IO) stripes extending across a first dimension of a first memory tile circuit of the multiple tiled memory circuits of each memory circuit area.

### Claim 5 (depends on 3)

The wafer-scale memory device of claim 3, wherein each channel includes 16 data signal terminations.

### Claim 6 (depends on 2)

The wafer-scale memory device of claim 2, wherein each memory tile circuit includes terminations of 64 channels of the DRAM memory, the terminations configured to couple with terminations of the wafer-scale processor.

### Claim 7 (depends on 6)

The wafer-scale memory device of claim 6, wherein the terminations are arranged in 8 input/output (IO) stripes extending across a first dimension of a first memory tile circuit of the multiple tiled memory circuits of each memory circuit area.

### Claim 8 (depends on 7)

The wafer-scale memory device of claim 7, wherein each channel includes 32 data signal terminations.

### Claim 9 (depends on 6)

The wafer-scale memory device of claim 6, wherein the DRAM memory is coupled to terminations of a first 32 channels of the 64 channels.

### Claim 10 (depends on 9)

The wafer-scale memory device of claim 9, wherein the wafer-scale memory device is a first wafer-scale memory device configured to couple with a second wafer-scale memory device to form a stack of wafer-scale memory devices; and
wherein the first wafer-scale memory device includes through silicon vias (TSVs) configured to route terminations of a second 32 channels to the second wafer-scale memory device of the stack of wafer-scale memory devices.

### Claim 11 (depends on 6)

The wafer-scale memory device of claim 6, wherein the terminations are arranged in 4 input/output (IO) stripes extending across a first dimension of a first memory tile circuit of the multiple tiled memory circuits of each memory circuit area.

### Claim 12 (depends on 11)

The wafer-scale memory device of claim 11, wherein each channel includes 32 data signal terminations.

### Claim 13 (depends on 12)

The wafer-scale memory device of claim 12, wherein the DRAM memory is coupled to terminations of a first 16 channels of the 64 channels.

### Claim 14 (depends on 13)

The wafer-scale memory device of claim 13, wherein the wafer-scale memory device is a first wafer-scale memory device configured to couple with a second wafer-scale memory device to form a stack of wafer-scale memory devices; and
wherein the first wafer-scale memory device includes through silicon vias (TSVs) configured to route terminations of a second 48 channels of the 64 channels to the second wafer-scale memory device of the stack of wafer-scale memory devices.

### Claim 15

A system comprising:
a processor; and
a wafer-scale memory stack coupled to the processor, the wafer-scale memory stack including a first wafer-scale memory device having a first substrate with a major surface area of more than 40,000 square millimeters (mm2), the first substrate having a first semiconductor memory circuit integrated therewith.

### Claim 16 (depends on 15)

The system of claim 15, wherein the wafer-scale memory stack includes a second wafer-scale memory device coupled with the first wafer-scale memory device, the second wafer-scale memory device including:
a second substrate with a major surface area of more than 40,000 mm2; and
a second semiconductor memory circuit integrated with the second substrate.

### Claim 17 (depends on 15)

The system of claim 15, including 20,000 channels configured to exchange information between the processor and the wafer-scale memory stack.

### Claim 18 (depends on 17)

The system of claim 17, wherein each channel of the 20,000 channels includes terminations for 32 data signals.

### Claim 19 (depends on 15)

The system of claim 15, wherein a bandwidth of the memory stack is equal to or greater than 300 terabytes per second.

### Claim 20 (depends on 15)

The system of claim 15, wherein the memory stack provides 336 gigabytes of addressable memory.