# US 2021/0240218 A1 · Data formatting circuit of a low voltage drive circuit data communication system

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- Number: US 2021/0240218 A1
- Document ID: US20210240218A1
- Status: Published application
- Kind: A1
- Application number: 17/217,822
- Filed: 2021-03-30
- Published: 2021-08-05
- Earliest claimed: 2019-02-04
- Assignees: Sigmasense, LLC.
- Applicants: SigmaSense, LLC.
- Inventors: Richard Stuart Seger, JR.; Daniel Keith Van Ostrand; Gerald Dale Morrison; Timothy W. Markison
- Web page: https://patentgrep.com/patent/US20210240218A1

## CPC

- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- H03K 19/17784: for supply voltage
- H03M 1/1255: {Synchronisation of the sampling frequency or phase to the input frequency or phase}
- H04B 1/40: Circuits
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04B: TRANSMISSION

## Abstract

A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert analog outbound data into an analog transmit signal and convert analog receive signals into analog inbound data, a transmit digital to analog circuit operable to convert transmit digital data into the analog outbound data, and a receive analog to digital circuit including an analog to digital converter, a digital filtering circuit, and a data formatting module. The data formatting module includes a sample and hold circuit operable to sample and hold an n-bit digital value of filtered digital data from the digital filtering circuit to produce an n-bit sampled digital data value, a digital to digital converter circuit operable to adjust formatting of the n-bit sampled digital data value to produce a formatted digital value, and a data packeting circuit operable to generate a packet of received digital data from a plurality of formatted digital values.

## Claims

### Claim 1

A low voltage drive circuit (LVDC) comprises:
a drive sense circuit operable to:
convert analog outbound data into an analog transmit signal that is transmitted on a bus;
receive an analog receive signal from the bus; and
convert the analog receive signal into analog inbound data;
a transmit digital to analog circuit operable to convert transmit digital data into the analog outbound data; and
a receive analog to digital circuit that includes:
an analog to digital converter operable to convert the analog inbound data into digital inbound data;
a digital filtering circuit operable to filter the digital inbound data to produce filtered digital data; and
a data formatting module including:
a sample and hold circuit operable to sample and hold an n-bit digital value of the filtered digital data to produce an n-bit sampled digital data value;
a digital to digital converter circuit operable to adjust formatting of the n-bit sampled digital data value to produce a formatted digital value; and
a data packeting circuit operable to generate a packet of received digital data from a plurality of formatted digital values.

### Claim 2 (depends on 1)

The LVDC of claim 1, wherein the data formatting module further comprises:
an interpreter operable to:
receive a plurality of n-bit sampled digital data values from the sample and hold circuit;
convert the plurality of n-bit sampled digital data values into a plurality of interpreted n-bit sampled digital data values; and
output, to the digital to digital converter circuit, the plurality of interpreted n-bit sampled digital data values on an interpreted n-bit sampled digital data value to interpreted n-bit sampled digital data value basis in accordance with a write clock.

### Claim 3 (depends on 2)

The LVDC of claim 2, wherein the interpreter converts the plurality of n-bit sampled digital data values into the plurality of interpreted n-bit sampled digital data values based on n-bit to binary data conversion.

### Claim 4 (depends on 2)

The LVDC of claim 2, wherein the interpreter outputs, to a first buffer of the LVDC, the plurality of interpreted n-bit sampled digital data values on the interpreted n-bit sampled digital data value to interpreted n-bit sampled digital data value basis in accordance with the write clock.

### Claim 5 (depends on 1)

The LVDC of claim 1, wherein the data formatting module further comprises:
a first buffer operable to:
receive a plurality of n-bit sampled digital data values from the sample and hold circuit, wherein the plurality of n-bit sampled digital data values includes the n-bit sampled digital data value;
store the of n-bit sampled digital data values on an n-bit sampled digital value by n-bit sampled digital value basis in accordance with a write clock; and
output a plurality of digital words on a digital word by digital word basis in accordance with a read clock, wherein a digital word of the plurality of digital words includes a set of n-bit sampled digital data values of the n-bit sampled plurality of digital data values.

### Claim 6 (depends on 5)

The LVDC of claim 5, wherein the digital to digital converter circuit is further operable to:
generate a plurality of formatted digital words from the plurality of digital words.

### Claim 7 (depends on 6)

The LVDC of claim 6, wherein the data formatting module further comprises:
a second buffer operable to:
store the plurality of formatted digital words on a formatted digital word by formatted digital word basis in accordance with the read clock of the first buffer to produce a plurality of buffered digital words; and
output the plurality of buffered digital words to the data packeting circuit on a buffered digital word by buffered digital word basis in accordance with a second read clock.

### Claim 8 (depends on 7)

The LVDC of claim 7, wherein the data packeting circuit is further operable to:
generate the packet to include a set of buffered digital words of the plurality of buffered digital words in accordance with a packet clock.