# US 2021/0240216 A1 · Output signal generation circuit

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- Number: US 2021/0240216 A1
- Document ID: US20210240216A1
- Status: Published application
- Kind: A1
- Application number: 17/236,650
- Filed: 2021-04-21
- Published: 2021-08-05
- Earliest claimed: 2016-08-18
- Assignees: Lapis Semiconductor Co., Ltd.
- Applicants: LAPIS Semiconductor Co., Ltd.
- Inventors: Kenjiro MATOBA; Kazuhiro YAMASHITA
- Web page: https://patentgrep.com/patent/US20210240216A1

## CPC

- G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom
- H03K 19/018521: {of complementary type, e.g. CMOS}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

## Claims

### Claim 1

An output signal generation circuit, comprising:
a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal;
a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width; and
an output circuit configured to output the second pulse signal,
wherein the second pulse generation circuit includes
a frequency division circuit configured to perform frequency division on a reference signal to generate a frequency division signal, and
a logic circuit configured to generate the second pulse signal from the first pulse signal and the frequency division signal, and
the second pulse generation circuit further receives third information, and includes a frequency control unit configured to control a frequency of the second pulse signal by changing a frequency division number of the frequency division signal such that the third information is superimposed on the second pulse signal.

### Claim 2 (depends on 1)

The output signal generation circuit according to claim 1, wherein the first and second information include control data for controlling different functions of an output device connected to the output signal generation circuit.

### Claim 3

An output signal generation circuit, comprising:
a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal;
a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width; and
an output circuit configured to output the second pulse signal,
wherein the second pulse generation circuit includes
a frequency division circuit configured to perform frequency division on a reference signal to generate a frequency division signal, and
a logic circuit configured to generate the second pulse signal from the first pulse signal and the frequency division signal, and
the second pulse generation circuit further receives third information and generates a third pulse signal in which the third information is superimposed on the first pulse signal,
the frequency division circuit generates the frequency division signal that is one of a first frequency and a second frequency, and
the logic circuit generates
the second pulse signal from the first pulse signal and the frequency division signal of the first frequency, and
the third pulse signal from the first pulse signal and the frequency division signal of the second frequency.

### Claim 4 (depends on 3)

The output signal generation circuit according to claim 3, wherein the first and second information include control data for controlling different functions of an output device connected to the output signal generation circuit.