# US 2021/0240043 A1 · Array substrate and manufacturing method thereof, display panel

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- Number: US 2021/0240043 A1
- Document ID: US20210240043A1
- Status: Published application
- Kind: A1
- Application number: 16/767,237
- Filed: 2019-12-18
- Published: 2021-08-05
- Earliest claimed: 2019-01-14
- Assignees: CHONGQING BOE OPTOE;ECTRONUICS TECHNOLOGY CO., LTD. and BOE TECHNOLOGY GROUP CO., LTD.
- Applicants: Boe Technology Group Co., Ltd.; Chongqing Boe Optoelectronics Technology Co., Ltd.
- Inventors: Xiaoyuan WANG; Wu WANG; Yan FANG; Shengxue WU
- Web page: https://patentgrep.com/patent/US20210240043A1

## CPC

- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- H10D 86/021: {of multiple TFTs}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/43: Layouts of interconnections
- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- G02F 1/134372: {for fringe field switching [FFS] where the common electrode is not patterned}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G02F 2201/40: Arrangements for improving the aperture ratio
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the present disclosure provides an array substrate and a manufacturing method thereof, a display panel. The array substrate includes: a base (10); a pixel electrode (50) and a thin film transistor disposed on the base (10); a passivation layer (16) covering the thin film transistor and the pixel electrode (50), the passivation layer (16) being provided with a transferring through hole (K1, K2) that simultaneously exposes the pixel electrode (50) and a drain electrode (15) or a source electrode (14) of the thin film transistor; a connection electrode (60) disposed on the passivation layer (16) and at the transferring through hole (K1, K2), the connection electrode (60) connected with the pixel electrode (50), and the drain electrode (15) or the source electrode (14) through the transferring through hole (K1, K2). The present disclosure realizes a connection between the drain electrode (15) or the source electrode (14) and the pixel electrode (50) by using one transferring through hole (K1, K2), which effectively reduces the number of through holes, increases an aperture ratio of the display panel, improves product quality and yield.

## Claims

### Claim 1

An array substrate, comprising
a base;
a pixel electrode and a thin film transistor, disposed on the base;
a passivation layer, covering the thin film transistor and the pixel electrode, the passivation layer being provided with a transferring through hole exposing the pixel electrode and a drain electrode or a source electrode of the thin film transistor simultaneously;
a connection electrode, disposed on the passivation layer and at the transferring through hole,
wherein the connection electrode is connected with the pixel electrode, and the drain electrode or the source electrode through the transferring through hole.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein an orthographic projection of the transferring through hole on the base overlaps with an orthographic projection of the pixel electrode on the base and an orthographic projection of the drain electrode or the source electrode on the base.

### Claim 3 (depends on 1, 2)

The array substrate according to claim 1 or 2, further comprising a gate line and a data line, wherein the thin film transistor comprises a gate electrode, an active layer, the source electrode and the drain electrode, the pixel electrode, the gate line and the gate electrode are disposed on the base, the pixel electrode, the gate line and the gate electrode are covered with a gate insulation layer, the active layer, the source electrode, the drain electrode and the data line are disposed on the gate insulation layer, and a conductive channel is formed between the source electrode and the drain electrode.

### Claim 4 (depends on 3)

The array substrate according to claim 3, wherein a first compensation block is disposed at a side of the connection electrode close to the gate line, an orthographic projection of the first compensation block on the base includes at least a portion of an orthographic projection of an edge of the drain electrode or the source electrode at a side adjacent to the gate line on the base, and/or, an second compensation block is disposed at a side of the connection electrode away from the gate line, an orthographic projection of the second compensation block on the base includes at least a portion of an orthographic projection of an edge of the source electrode or the drain electrode at a side away from the gate line on the base.

### Claim 5 (depends on 4)

The array substrate according to claim 4, wherein the first compensation block extends from a mainbody of the connection electrode towards the gate line, the second compensation block extends from the mainbody of the connection electrode to a direction away from the gate line, and sizes of the first compensation block and the second compensation block are smaller than a size of the mainbody in a direction parallel to a direction of the gate line.

### Claim 6 (depends on 5)

The array substrate according to claim 5, wherein an orthographic projection of the connection electrode on the base covers an orthographic projection of an overlapped region between the drain electrode or the source electrode and the pixel electrode on the base.

### Claim 7 (depends on 4)

The array substrate according to claim 4, wherein shapes of the first compensation block and/or the second compensation block comprises a rectangle, a trapezoid, a semicircle or a semi-ellipse.

### Claim 8 (depends on 1)

The array substrate according to claim 1, wherein the transferring through hole comprises a first through hole portion and a second through hole portion, the first through hole portion exposes the drain electrode, the second through hole portion exposes the pixel electrode.

### Claim 9 (depends on 1)

A display panel comprising the array substrate according to claim 1.

### Claim 10

A manufacturing method of an array substrate, comprising:
forming a pixel electrode and a thin film transistor;
forming a passivation layer covering the thin film transistor, the passivation layer being provided with a transferring through hole that exposes the pixel electrode and a drain electrode or a source electrode of the thin film transistor simultaneously;
forming a connection electrode on the passivation layer and at the transferring through hole, wherein the connection electrode is simultaneously connected with the pixel electrode, and the drain electrode or the source electrode through the transferring through hole.

### Claim 11 (depends on 10)

The manufacturing method according to claim 10, wherein the forming a pixel electrode and a thin film transistor on the base comprises:
forming the pixel electrode, a gate line and a gate electrode by means of one patterning process;
forming a gate insulation layer, an active layer, a source electrode, a drain electrode and a data line by means of one patterning process, forming a conductive channel between the source electrode and the drain electrode.

### Claim 12 (depends on 10)

The manufacturing method according to claim 10, wherein a first compensation block is disposed at a side of the connection electrode close to the gate line, an orthographic projection of the first compensation block on the base includes at least a portion of an orthographic projection of an edge of the drain electrode or the source electrode at a side adjacent to the gate line on the base, and/or, a second compensation block is disposed at a side of the connection electrode away from the gate line, an orthographic projection of the second compensation block on the base includes at least a portion of an orthographic projection of an edge of the drain electrode or the source electrode at a side away from the gate line on the base.

### Claim 13 (depends on 12)

The manufacturing method according to claim 12, wherein the first compensation block extends from a mainbody of the connection electrode towards the gate line, the second compensation block extends from the mainbody of the connection electrode to a direction away from the gate line, and sizes of the first compensation block and the second compensation block are smaller than a size of the mainbody in a direction parallel to a direction of the gate line.

### Claim 14 (depends on 10)

The manufacturing method according to claim 10, wherein the transferring through hole comprises a first through hole portion and a second through hole portion, the first through hole portion exposes the drain electrode, and the second through hole portion exposes the pixel electrode.

### Claim 15 (depends on 11)

The manufacturing method according to claim 11, wherein the forming a pixel electrode, a gate line and a gate electrode by means of one patterning process comprises:
depositing a first transparent conductive film and a first metal film on the base sequentially;
coating a layer of photoresist on the first metal film, gradient exposing and developing the photoresist using a halftone mask or a gray tone mask, forming an unexposed region at a location where the gate line and the gate electrode to be formed are located, the unexposed region being with a photoresist having a first thickness, forming a partially exposed region at a location where the pixel electrode to be formed is located, the partially exposed region being with a photoresist having a second thickness, forming a fully exposed region at other locations without a photoresist, and the first thickness is greater than the second thickness;
etching away the first metal film and the first transparent conductive film in the fully exposed region by means of a first etching process;
removing the photoresist in the partially exposed region by means of an ashing process, exposing the first metal film; and
etching away the first metal film in the partially exposed region by means of a second etching process, removing a remaining portion of the photoresist and forming the pixel electrode, the gate line and the gate electrode on the base.

### Claim 16 (depends on 11)

The manufacturing method according to claim 11, wherein the forming a gate insulation layer, an active layer, a source electrode, a drain electrode and a data line, forming a conductive channel between the source electrode and the drain electrode by means of one patterning process comprises:
depositing a gate insulation film, a semiconductor film and a second metal film on the base on which the pixel electrode, the gate line and the gate electrode are formed;
coating a layer of photoresist on the second metal film, gradient exposing and developing the photoresist using a halftone mask or a gray tone mask, forming an unexposed region at a location where the source electrode, the drain electrode and the data line to be formed are located, the unexposed region being with a photoresist having a first thickness, forming a partially exposed region at a location where the conductive channel to be formed is located, the partially exposed region being with a photoresist having a second thickness, forming a fully exposed region at other locations without a photoresist, and the first thickness is greater than the second thickness;
etching away the second metal film and the semiconductor film in the fully exposed region by means of a first etching process;
removing the photoresist in the partially exposed region by means of an ashing process, exposing the second metal film;
etching away the second metal film in the partially exposed region by means of a second etching process, removing a remaining portion of the photoresist, forming the gate insulation layer, the active layer, the source electrode, the drain electrode and the data line, forming a conductive channel between the source electrode and the drain electrode.

### Claim 17 (depends on 10)

The manufacturing method according to claim 10, wherein the forming the passivation layer covering the thin film transistor, and the passivation layer being provided with a transferring through hole that exposes the pixel electrode and a drain electrode or a source electrode of the thin film transistor simultaneously comprises:
depositing a passivation film on a base on which the thin film transistor and the pixel electrode are formed;
coating a layer of photoresist on the passivation film, exposing and developing the photoresist using a monotone mask, forming an exposed region at a location of the transferring through hole without the photoresist, forming an unexposed region at other locations in which the photoresist is remained;
etching away the passivation film and the gate insulation layer in the fully exposed region by means of an etching process, forming the passivation layer in which the transferring through hole is formed and the transferring through hole exposing a drain electrode and a pixel electrode simultaneously,
wherein the transferring through hole comprises a first through hole portion and a second through hole portion, the passivation film in the first through hole portion is etched away and the drain electrode is exposed, and the passivation film and the gate insulation layer in the second through hole portion are etched away and the pixel electrode is exposed.

### Claim 18 (depends on 2)

The array substrate according to claim 2, wherein the transferring through hole comprises a first through hole portion and a second through hole portion, the first through hole portion exposes the drain electrode, the second through hole portion exposes the pixel electrode.

### Claim 19 (depends on 3)

The array substrate according to claim 3, wherein the transferring through hole comprises a first through hole portion and a second through hole portion, the first through hole portion exposes the drain electrode, the second through hole portion exposes the pixel electrode.

### Claim 20 (depends on 4)

The array substrate according to claim 4, wherein the transferring through hole comprises a first through hole portion and a second through hole portion, the first through hole portion exposes the drain electrode, the second through hole portion exposes the pixel electrode.