# US 2021/0239751 A1 · Through-silicon via detecting circuit, detecting methods and integrated circuit thereof

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- Number: US 2021/0239751 A1
- Document ID: US20210239751A1
- Status: Published application
- Kind: A1
- Application number: 17/238,476
- Filed: 2021-04-23
- Published: 2021-08-05
- Earliest claimed: 2018-11-09
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: You-Hsien LIN; Yi-Jun LU; Cheng-Jer YANG
- Web page: https://patentgrep.com/patent/US20210239751A1

## CPC

- G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)}
- G01R 31/28: Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00})
- G01R 31/2882: {Testing timing characteristics}
- G01R 31/2843: {In-circuit-testing}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A TSV detecting circuit, TSV detecting methods, and an integrated circuit thereof are disclosed by the present disclosure. The TSV detecting circuit includes a first detecting module includes: a first comparison unit; a first input unit, for transmitting an input signal to a first input of the first comparison unit controlled by a first clock signal; a first switching unit for transmitting a signal of a first node to a second input of the first comparison unit controlled by a first detection control signal, the first node coupled to a first terminal of the TSV; and a second detecting module includes: a second input unit for transmitting the input signal to a second node controlled by a second clock signal; a second switching unit for transmitting a signal of the second node to a second terminal of the TSV controlled a second detection control signal.

## Claims

### Claim 1

A through-silicon via (TSV) detecting circuit, comprising:
a first detecting module, including:
a first comparison unit;
a first input unit, configured to transmit an input signal to a first input of the first comparison unit under a control of a first clock signal; and
a first switching unit, configured to transmit a signal of a first node to a second input of the first comparison unit under a control of a first detection control signal, the first node being coupled to a first terminal of the TSV; and
a second detecting module, including:
a second input unit, configured to transmit the input signal to a second node under a control of a second clock signal; and
a second switching unit, configured to transmit a signal of the second node to a second terminal of the TSV under a control of a second detection control signal.

### Claim 2 (depends on 1)

The TSV detecting circuit of claim 1, wherein the first input unit comprises:
a first flip-flop, comprising an input coupled to the input signal, an output coupled to the first input of the first comparison unit, and a clock terminal coupled to the first clock signal.

### Claim 3 (depends on 2)

The TSV detecting circuit of claim 2, wherein the first input unit further comprises:
a first selector, comprising a first input coupled to the input signal, a second input coupled to an output of the first comparison unit, a control terminal coupled to a first selection control signal, and an output coupled to the input of the first flip-flop.

### Claim 4 (depends on 3)

The TSV detecting circuit of claim 3, wherein the first detecting module further comprises:
a third switching unit, comprising a first terminal coupled to the output of the first flip-flop, a second terminal coupled to the first node, and a control terminal coupled to the first detection control signal.

### Claim 5 (depends on 1)

The TSV detecting circuit of claim 1, wherein the second input unit comprises:
a second flip-flop, comprising an input coupled to the input signal, an output coupled to a second node, and a clock terminal coupled to the second clock signal.

### Claim 6 (depends on 5)

The TSV detecting circuit of claim 5, wherein the second input unit further comprises:
a second selector, comprising a first input coupled to the input signal, a control terminal coupled to a second selection control signal, and an output coupled to the input of the second flip-flop.

### Claim 7 (depends on 6)

The TSV detecting circuit of claim 6, wherein the second detecting module further comprises:
a fourth switching unit, comprising a first terminal coupled to the second terminal of the TSV and a control terminal coupled to the second detection control signal; and
a second comparison unit, comprising a first input coupled to a second terminal of the fourth switching unit, a second input coupled to the second node, and an output coupled to a second input of the second selector.

### Claim 8 (depends on 7)

The TSV detecting circuit of claim 7, wherein:
the first detecting module is disposed on a first chip layer;
the second detecting module is disposed on a second chip layer; and
the first chip layer and the second chip layer are connected by at least one TSV.

### Claim 9 (depends on 8)

The TSV detecting circuit of claim 8, wherein the at least one TSV includes a plurality of sequentially connected TSVs.

### Claim 10 (depends on 8)

The TSV detecting circuit of claim 8, wherein:
a plurality of first detecting modules is sequentially disposed on the first chip layer, and the output of the first flip-flop of each first detecting module is connected to the input of an immediately succeeding first detection module; and
a plurality of second detecting modules are sequentially disposed on the second chip layer, and the output of the second flip-flop of each second detecting module is connected to the input of an immediately succeeding second detection module.

### Claim 11 (depends on 10)

The TSV detecting circuit of claim 10, further comprising:
a third comparison unit, wherein the outputs of a plurality of first comparison units of the plurality of first detecting modules are respectively connected to inputs of the third comparison unit.

### Claim 12 (depends on 1)

The TSV detecting circuit of claim 1, wherein each of the comparison units includes at least an XOR gate.

### Claim 13 (depends on 1)

The TSV detecting circuit of claim 1, wherein:
the first switching unit is an N-type MOS transistor and the second switching unit is a P-type MOS transistor; or
the first switching unit is a P-type MOS transistor and the second switching unit is an N-type MOS transistor.

### Claim 14 (depends on 1)

The TSV detecting circuit of claim 1, wherein each of the first switching unit and the second switching unit is a complementary metal oxide semiconductor (CMOS) transmission gate.

### Claim 15 (depends on 1)

The TSV detecting circuit of claim 1, wherein the TSV detecting circuit is configured to:
detect a defected TSV in a plurality of chip layers;
determine a location of the defected TSV; and
shield the defected TSV with a redundant TSV disposed in the plurality of chip layers.

### Claim 16 (depends on 15)

The TSV detecting circuit of claim 15, wherein:
the TSV detecting circuit is further configured to detect and shield the defected TSV located anywhere in the IC, such as between a topmost chip layer and a layer immediately beneath the topmost chip layer (the “top TSV”), between a bottommost chip layer and a layer immediately above that bottommost layer (the “bottom TSV”), or between two chip layers wherein neither is the topmost chip layer or the bottommost chip layer (the “middle TSV”).

### Claim 17

A TSV detecting method, comprising:
transmitting, according to a first clock signal, an input signal to a first input unit and further to a first input of a first comparison unit, wherein the TSV detecting circuit comprises a first detecting module and a second detecting module, the first detecting module comprises the first input unit, a first switching unit, and the first comparison unit, and the first switching unit is configured to transmit a signal of a first node coupled to a first terminal of a TSV to a second input of the first comparison unit under a control of a first detection control signal;
transmitting, by the TSV detecting circuit, according to a second clock signal, the input signal to a second input unit and further to a second node, wherein the second detecting module comprises the second input unit and a second switching unit, and the second switching unit is configured to transmit a signal of the second node to a second terminal of the TSV under a control of a second detection control signal;
turning on the first switching unit by the first detection control signal and turning on the second switching unit by the second detection control signal, and transmitting the input signal to the second input of the first comparison unit through the second switching unit, the TSV, and the first switching unit; and
comparing, by the TSV detecting circuit, signals input into the first input and the second input of the first comparison unit, and outputting a comparison result.

### Claim 18 (depends on 17)

The TSV detecting method of claim 17, further comprising:
sequentially transmitting, according to the second clock signal, the input signal to a plurality of second input units and further to a plurality of corresponding second nodes;
sequentially transmitting, according to the first clock signal, the input signal to a plurality of first input units and further to first inputs of a plurality of first comparison units;
turning on a plurality of first switching units by the first detection control signal and turning on a plurality of second switching units by the second detection control signal, wherein the input signal is respectively transmitted to second inputs of a plurality of first comparison units through the plurality of second switching units, a plurality of TSVs coupled with the plurality of second switching units and the plurality of first switching units;
comparing signals input into the first input and the second input of each of the plurality of first comparison units, and outputting a plurality of first comparison results.

### Claim 19 (depends on 18)

The TSV detecting method of claim 18, further comprising:
respectively transmitting the output signals of the plurality of first comparison units to a third comparison unit, wherein the third comparison unit compares the output signals of the plurality of first comparison units, and outputs a comparison result.

### Claim 20 (depends on 17)

The TSV detecting method of claim 17, further comprising:
detecting a defected TSV in a plurality of chip layers;
determining a location of the defected TSV; and
shielding the defected TSV with a redundant TSV disposed in the plurality of chip layers;
wherein the defected TSV located anywhere in the IC, such as between a topmost chip layer and a layer immediately beneath the topmost chip layer (the “top TSV”), between a bottommost chip layer and a layer immediately above that bottommost layer (the “bottom TSV”), or between two chip layers wherein neither is the topmost chip layer or the bottommost chip layer (the “middle TSV”).