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US 2021/0233604 A1Published application
Semiconductor memory devices, memory systems, and methods of operating semiconductor memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsKyung-Ryun KIM, Yoon-Na OH, Hyung-Jin KIM, Hui-Kap YANG, Jang-Woo RYU
Life of this patent
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Abstract
A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
Claims19
A memory device, comprising:
- a plurality of memory blocks, each memory block including a plurality of columns of normal memory cells;
- at least one redundancy block, each redundancy block including a plurality of columns of redundancy memory cells;
- and
- a repair control circuit configured to:
- replace a first normal memory cell in a first column of a first memory block of the plurality of the memory blocks with a second normal memory cell in a second column of the first memory block,
- replace the second normal memory cell of the second column of the first memory block with a third normal memory cell in a first column of a second memory block of the plurality of the memory blocks, and
- replace the third normal memory cell in the first column of the second memory block with a fourth normal memory cell in a first column of a third memory block of the plurality of the memory blocks or a first redundancy memory cell in a first column of a first redundancy block of the at least one redundancy block,
- wherein the second column of the first memory block, the first column of the second memory block and the first column of the third memory block have the same relative location with respect to the columns of their respective memory blocks.
5 more elements
A memory device, comprising:
- a plurality of memory blocks, each memory block including a plurality of columns of normal memory cells;
- at least one redundancy block, each redundancy block including a plurality of columns of redundancy memory cells;
- and
- a repair control circuit configured to:
- replace a first normal memory cell in a first column of a first memory block of the plurality of the memory blocks with a second normal memory cell in a second column of the first memory block;
- and
- replace a third normal memory cell in a first column of a second memory block of the plurality of the memory blocks with a fourth normal memory cell in a second column of the second memory block,
- wherein the first column of the first memory block and the first column of the second memory block have the same relative location with respect to the columns of their respective memory blocks, and
- the second column of the first memory block and the second column of the second memory block have a different relative location with respect to the columns of their respective memory blocks.
6 more elements
A memory device comprising:
- a plurality of memory blocks, each memory block including a plurality of columns of normal memory cells;
- at least one redundancy block, each redundancy block including a plurality of columns of redundancy memory cells;
- and
- a repair control circuit configured to:
- replace a first normal memory cell in a first column of a first memory block of the plurality of the memory blocks with a second normal memory cell in a second column of the first memory block;
- replace the second normal memory cell of the second column of the first memory block with a third normal memory cell in a first column of a second memory block of the plurality of the memory blocks;
- and
- replace the third normal memory cell in the first column of the second memory block with a fourth normal memory cell in a first column of a third memory block of the plurality of the memory blocks or a first redundancy memory cell in a first column of a first redundancy block of the at least one redundancy block,
- wherein the first column of the third memory block and the first column of the first redundancy block have a different relative location with respect to the columns of their respective memory blocks.
6 more elements
Dependencies are inferred from the claim text.