Preemptive read refresh in memories with time-varying error rates
AssigneeMicron Technology, Inc.
InventorsTingjun Xie, Zhengang Chen
Life of this patent
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Abstract
A processing device in a memory sub-system determines a write-to-read delay time for a segment of a memory device read during a first read operation using a first read voltage level. The processing device further determines that the write-to-read delay time is associated with a second read voltage level and performs a read refresh operation on at least a portion of the segment of the memory device using the second read voltage level.
Claims20
A system comprising:
- a memory device;
- and
- a processing device, operatively coupled with the memory device, to perform operations comprising:
- determining a write-to-read delay time for a segment of the memory device read during a first read operation using a first read voltage level;
- determining that the write-to-read delay time is associated with a second read voltage level;
- and
- performing a read refresh operation on at least a portion of the segment of the memory device using the second read voltage level.
A method of operation of a memory sub-system comprising:
- determining a write-to-read delay time for a segment of a memory device of the memory sub-system read during a first read operation using a first read voltage level;
- determining that the write-to-read delay time is associated with a second read voltage level;
- and
- performing a read refresh operation on at least a portion of the segment of the memory device using the second read voltage level.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- determining a write-to-read delay time for a segment of the memory device read during a first read operation using a first read voltage level;
- determining that the write-to-read delay time is associated with a second read voltage level;
- and
- performing a read refresh operation on at least a portion of the segment of the memory device using the second read voltage level.
Dependencies are inferred from the claim text.