Erasing memory

A memory, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• and
• a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to perform a method comprising:
• applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells of the plurality of strings of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells;
• and
• increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

A method of operating a memory, comprising:

• applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells;
• increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate;
• and
• when the voltage level applied to the first node reaches a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.

A memory, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• and
• a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to perform a method comprising:
• applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells of the plurality of strings of series-connected memory cells;
• increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate;
• and
• when the voltage level applied to the first node reaches a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.

A memory, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• and
• a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
• apply a first voltage level to a first node selectively connected to a string of series-connected memory cells of the plurality of strings of memory cells while applying the first voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells;
• maintain the voltage level applied to the first node at the first voltage level while decreasing the voltage level applied to the control gate of the transistor to a second voltage level;
• and
• for each time period of a plurality of successive time periods:
• increase the voltage level applied to the first node by a corresponding magnitude for that time period;
• and
• increase the voltage level applied to the control gate of the transistor by the corresponding magnitude for that time period.