Non volatile static random access memory device and corresponding control method

The integrated circuit according to claim ii, wherein the write circuitry is configured to generate, among the first write signals, a third set of power voltages on the power lines of the selected memory word adapted to cease function of the volatile memory cells, then a datum signal to be stored on the common node imposed via the bit line of the memory points of the selected memory word, and then a first set of power voltages on the power lines, adapted for a functional powering of the volatile memory cells.

A method for commanding a memory device including at least one memory point comprising a volatile memory cell and a single non-volatile memory cell coupled together to a common node, a single selection transistor coupled between the common node and a single bit line, a first output of the volatile memory cell being coupled to the common node, and a second output of the volatile memory cell, complementary to the first output, not being connected to any node outside the volatile memory cell, a memory plane including a plurality of the memory points arranged in at least one memory word, the method comprising:

• storing a power status for each memory word, a first value of the power status being representative of a non-operating state of the volatile memory cells of the respective memory word, and a second value of the power status being representative of an operating state of the volatile memory cells of the respective memory word.