Bit-line voltage generation circuit for a non-volatile memory device and corresponding method

A voltage generation circuit for a non-volatile memory device comprising a memory array having a plurality of memory cells coupled to respective wordlines and local bit-lines, each memory cell comprising a storage element and a selector element including a bipolar transistor coupled to the storage element and configured to selectively enable flow of a cell current during reading or verifying operations, wherein a base terminal of the selector element is coupled to a respective wordline, wherein a sense amplifier stage is associated with the local bit-lines via a column decoder, wherein the sense amplifier stage comprises at its input respective biasing transistors each having a control terminal, and wherein a driver stage is coupled to each wordline for biasing thereof during the reading or verifying operations, wherein the voltage generation circuit is configured to:

• generate a cascode voltage for the control terminals of the biasing transistors based on a reference voltage, wherein the reference voltage is a function of an emulation of a respective voltage drop on the driver stage, on the wordline, and on the memory cell, as a result of a current associated with the corresponding selector element.