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US 2021/0233574 A1Published application
Page buffer and memory device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsYong Sung CHO, Jeung Hwan PARK, Jong Min KIM, Jung Kwan KIM
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Abstract
A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.
Claims20
A memory device comprising:
- a memory cell array including a plurality of memory blocks having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings;
- a plurality of page buffers connected to the plurality of bit lines, and arranged in a first direction and in a second direction, orthogonal to the first direction, wherein each of the plurality of page buffers comprises
- a plurality of transistors including a pass transistor,
- a sensing line connected to at least one transistor other than the pass transistor, among the plurality of transistors, and
- a data transfer line connected to at least another transistor other than the at least one transistor connected to the sensing line;
- and
- a monitoring circuit connected to at least one page buffer among the plurality of page buffer,
- wherein the pass transistor included in the at least one page buffer connected to the monitoring circuit is connected between the data transfer line and the monitoring circuit, and each of the other pass transistors are connected between the data transfer line of a page buffer including the each of the other pass transistors and the data transfer line of another page buffer.
5 more elements
A memory device comprising:
- a memory cell array having a plurality of memory cell strings, and a plurality of first to n-th bit lines connected to at least one of the plurality of memory cell strings;
- a plurality of first to n-th page buffers connected to the plurality of first to n-th bit lines, sequentially arranged in a first direction, and performing a transferring operation to transfer data between a plurality of latch circuits using first signals applied to a conductive line connected or separated from each other by a pass transistor;
- and
- a monitoring circuit connected to the n-th page buffer, and performing a monitoring operation to monitor data stored in at least some of the plurality of first to n-th page buffers using second signals applied to the same conductive line.
1 more element
A memory device comprising:
- a memory cell region including a first metal pad;
- a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
- a memory cell array in the memory cell region including a plurality of memory blocks having a plurality of memory cell strings, and a plurality of bit lines connected to the plurality of memory cell strings;
- a plurality of page buffers in the peripheral circuit region connected to the plurality of bit lines, and arranged in a first direction and in a second direction, orthogonal to the first direction, wherein each of the plurality of page buffers comprises
- a plurality of transistors including a pass transistor configured to set a connection with another page buffer,
- a sensing line connected to at least one transistor other than the pass transistor, among the plurality of transistors, and
- a data transfer line connected to at least another transistor other than the at least one transistor connected to the sensing line;
- and
- a monitoring circuit in the peripheral circuit region connected to at least one page buffer among the plurality of page buffer.
6 more elements
Dependencies are inferred from the claim text.