Method and apparatus for dynamically changing display clock frequency
AssigneeIntel Corporation
InventorsPrashant Chaudhari, Arthur Runyan, Michael Derr, Jonathan Oder
Life of this patent
Estimating the term…
Abstract
Upon external display configuration change, a graphics display driver or any suitable hardware or software modifies the clock frequency of the processor core (e.g., graphics processor core) display engine. The graphics display driver or any suitable hardware or software reprograms the core display clock PLL (CDCLK PLL) to a new frequency, without any dead clocks during such frequency change. A divide-by-2 divider changes the frequency of the PLL on the fly or dynamically. The technique may not require the PLL to be turned off and turned back again at all.
Claims21
An apparatus comprising:
- a display controller to control one or more displays, including an embedded display;
- a phase locked loop (PLL) coupled to the display controller, wherein the PLL provides a clock with an adjustable frequency to the display controller;
- and
- logic to modify the frequency of the clock in accordance with a resolution of a non-embedded display coupled to the apparatus, wherein the PLL is configured to remain locked when the logic modifies the frequency of the clock.
A machine-readable storage media having machine readable instructions, that when executed, cause one or more processors to cause a machine to perform an operation comprising:
- controlling, via a display controller, one or more displays, including an embedded display;
- providing, via a phase locked loop (PLL) coupled to the display controller, a clock with an adjustable frequency to the display controller;
- modifying, via a logic, the frequency of the clock in accordance with a resolution of a non-embedded display;
- and
- maintaining lock for the PLL when the logic modifies the frequency of the clock.
A system comprising:
- a memory;
- a graphics processor coupled to the memory, wherein the graphics processor includes:
- a display controller to control one or more displays, including a first display;
- a phase locked loop (PLL) coupled to the display controller, wherein the PLL provides a clock with an adjustable frequency to the display controller;
- and
- logic to modify the frequency of the clock in accordance with a resolution of a second display communicatively coupled to the graphics processor, wherein the PLL is configured to remain locked when the logic modifies the frequency of the clock;
- and
- an antenna communicatively coupled to the graphics processor.
Dependencies are inferred from the claim text.