Display controller, display control method, display control system, display apparatus

A display controller comprising:

• n field-programmable gate arrays (FPGAs), wherein n is an integer greater than 1;
• wherein a respective one of the n FPGAs comprises a first input circuit and an output circuit and a first process circuit connected between the first input circuit and the output circuit;
• wherein the first input circuit is configured to receive a respective one first sub-image corresponding to the respective one of the n FPGAs, wherein n first sub-images respectively corresponding to the n FPGAs is combined to form one frame of initial image;
• wherein the first process circuit is configured to enhance image-resolution of the respective one first sub-image corresponding to the respective one of the n FPGAs to obtain a respective one second sub-image corresponding to the respective one of the n FPGAs;
• and
• wherein the output circuit is configured to deliver the respective one second sub-image corresponding to the respective one of the n FPGAs to a timing-controller.