Tessellation Hardware Subdivision of Patches Into Sub-Patches
AssigneeImagination Technologies Limited
InventorsPeter Malcolm Lacey, Simon Fenney
Life of this patent
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Abstract
Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
Claims20
A hardware tessellation unit comprising a patch stack, a sub-division decision logic block and a sub-division logic block, wherein:
- the patch stack is arranged to store patch data describing one or more initial patches and a plurality of sub-patches and to output the patch data;
- the sub-division decision logic block is arranged to determine, from the patch data received from the patch stack, whether the initial patch or sub-patch for which the patch data is received is to be sub-divided, and to output the patch data to the sub-division logic block in response to determining that the initial patch or sub-patch is to be sub-divided;
- the sub-division logic block is configured to receive the patch data from the sub-division decision logic block, and arranged to sub-divide the initial patch or sub-patch for which the patch data is received;
- and
- an order flip logic block comprises:
- (i) an input configured to receive the patch data for each of the sub-patches output by the sub-division block, (ii) an output, and (iii) hardware logic arranged to control the order in which the patch data for each of the sub-patches is output via the output based on one or more stored values.
A hardware tessellation unit comprising:
- an initial patch selection logic block arranged to select a patch data for one of a plurality of initial patches based on one or more bits of a primitive or vertex ID;
- a sub-division logic block configured to receive patch data, and to sub-divide the initial patch or sub-patch for which patch data is received;
- a sub-patch selection logic block arranged to select patch data for one of the sub-patches formed by sub-division in the sub-division logic block based on one or more bits of the primitive or vertex ID;
- an order flip logic block comprising:
- (i) an input configured to receive the patch data for each of the sub-patches output by the sub-division block, (ii) an output, and (iii) hardware logic arranged to control the order in which the patch data for each of the sub-patches is output via the output based on one or more stored values;
- and
- an end of ID logic block configured to receive patch data for an initial patch from the initial patch selection logic block, to receive patch data for the selected sub-patches from the sub-patch selection logic block, and to determine, from an ID for the initial patch or sub-patch, whether the initial patch or sub-patch is to be sub-divided.
A hardware tessellation unit, comprising:
- an initial patch selection logic block arranged to select a patch data for one of the plurality of patches based on one or more bits of the primitive or vertex ID;
- a sub-division logic block configured to receive patch data, and to sub-divide the initial patch or sub-patch for which patch data is received;
- a sub-patch selection logic block arranged to select patch data for one of the sub-patches formed by sub-division in the sub-division logic block based on one or more bits of the ID;
- an end of ID logic block configured to receive patch data for an initial patch from the initial patch selection logic block, to receive patch data for the selected sub-patches from the sub-patch selection logic block, and to determine, from an ID for the initial patch or sub-patch, whether the initial patch or sub-patch is to be sub-divided;
- and
- a corner and middle vertex check logic block comprising:
- (i) a first input configured to receive a vertex ID, (ii) a second input configured to receive domain vertices from the pre-processing block, (iii) hardware logic arranged to compare the received ID to a known set of IDs corresponding to the vertices of the initial patches and determine if there is a match, and (iv) an output configured to output the domain vertex in response to determining that there is a match between the received ID and an ID in the known set of IDs.
Dependencies are inferred from the claim text.