Data Flow Architecture for Processing with Memory Computation Modules

A memory computation module (MCM) circuit, comprising:

• a plurality of memory arrays configured to perform mathematical operations on a data set;
• an interface unit configured to parse input data and store parsed input data to a buffer;
• a convolution node configured to determine a distribution of the data set among the plurality of memory arrays;
• one or more alignment buffers configured to enable multiple memory arrays to be written with data of the data set simultaneously using a single memory word read;
• and
• an output node configured to process a computed data set output by the plurality of memory arrays.

A method of computation, comprising:

• at a memory computation module (MCM) comprising a plurality of memory arrays and a module controller configured to program the plurality of memory arrays to perform mathematical operations on a data set:
• parsing input data via a reader node;
• storing the input data to a buffer via a buffer node;
• reading the input data via a scanner reader node;
• at a convolution node, determining a distribution of a data set among the plurality of memory arrays, the data set corresponding to the input data;
• at the plurality of memory arrays, processing the data set to generate a data output.

A method of compiling a neural network, comprising:

• parsing a computation graph of nodes having a plurality of different node types into its constituent nodes;
• performing shape inference on input and output tensors of the nodes to specify a computation graph representation of vectors and matrices on which processor hardware is to operate;
• generating a modified computation graph representation, the modified computation graph representation being configured to be operated by a plurality of memory computation modules (MCMs);
• memory mapping the modified computation graph representation by providing addresses through which MCMs can transfer data;
• and
• generating a runtime executable code based on the modified computation graph representation.