Shared scratchpad memory with parallel load-store

A method for performing computations to generate an output for a layer of a neural network comprising a plurality of neural network layers using a circuit configured to implement the neural network, the method comprising:

• providing, from a first memory, data used to generate an output for a neural network layer;
• storing vectors of values at a first processor core of the circuit using a first vector memory of the first processor core, wherein the first vector memory is configured to store first vector values derived from the data provided by the first memory;
• storing vectors of values at a second processor core of the circuit using a second vector memory of the second processor core, wherein the second vector memory is configured to store second vector values derived from the data provided by the first memory;
• routing, using a first direct memory access (DMA) data path of a shared memory in the circuit, data communications comprising at least the first vector values between the shared memory and the first vector memory included in the first processor core;
• routing, using a second direct memory access (DMA) data path of the shared memory in the circuit, data communications comprising at least the second vector values between the shared memory and the second vector memory included in the second processor core;
• routing, using a first load-store data path of the shared memory, data communications comprising third vector values between the shared memory and a first vector register included in the first processor core;
• routing, using a second load-store data path of the shared memory, data communications comprising fourth vector values between the shared memory and a second vector register included in the second processor core;
• and
• generating, by a matrix computation unit, accumulated values corresponding to the output for the neural network layer using the respective first and third vector values that are routed to the matrix computation unit in parallel along the first load-store data path and the first DMA data path of the shared memory, respectively;
• wherein the first and second DMA data paths and the first and second load-store data paths are established using wired connections, wherein at least a portion of the wired connections are shared between the first DMA data path and the second DMA data path;
• and at least another portion of the wired connections are shared between the first load-store data path and the second load-store data path.

A non-transitory machine-readable storage device for implementing a neural network having multiple neural network layers on a circuit used to perform neural network computations and for storing instructions that are executable by a processing device to cause performance of operations comprising:

• providing, from a first memory, data used to generate an output for a neural network layer;
• storing vectors of values at a first processor core of the circuit using a first vector memory of the first processor core, wherein the first vector memory is configured to store first vector values derived from the data provided by the first memory;
• storing vectors of values at a second processor core of the circuit using a second vector memory of the second processor core, wherein the second vector memory is configured to store second vector values derived from the data provided by the first memory;
• routing, using a first direct memory access (DMA) data path of a shared memory in the circuit, data communications comprising at least the first vector values between the shared memory and the first vector memory included in the first processor core;
• routing, using a second direct memory access (DMA) data path of the shared memory in the circuit, data communications comprising at least the second vector values between the shared memory and the second vector memory included in the second processor core;
• routing, using a first load-store data path of the shared memory, data communications comprising third vector values between the shared memory and a respective vector register included in the first processor core;
• routing, using a second load-store data path of the shared memory, data communications comprising fourth vector values between the shared memory and a second vector register included in the second processor core;
• and
• generating, by a matrix computation unit, accumulated values corresponding to the output for the neural network layer using the respective first and third vector values that are routed to the matrix computation unit in parallel along the first load-store data path and the first DMA data path of the shared memory, respectively;
• wherein the first and second DMA data paths and the first and second load-store data paths are established using wired connections, wherein at least a portion of the wired connections are shared between the first DMA data path and the second DMA data path;
• and at least another portion of the wired connections are shared between the first load-store data path and the second load-store data path.