Multi-Chip Module Rate Adjustment
AssigneeMellanox Technologies Tlv Ltd.
InventorsGuy Lederman, Ran Ravid, Asaf Horev
Life of this patent
Estimating the term…
Abstract
A Multi-Chip-Module (MCM) includes an MCM substrate and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate. The DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced date and durations of the first time periods and the second time periods, are preset.
Claims13
A Multi-Chip-Module (MCM), comprising:
- an MCM substrate;
- and
- at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate,
- wherein the DPIC is configured to send data to the DCIC over the high-speed bus having the fixed data rate, by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced data and durations of the first time periods and the second time periods, are preset.
The A Multi-Chip-Module (MCM), comprising:
- an MCM substrate;
- and
- at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate,
- wherein the DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced data and durations of the first time periods and the second time periods, are preset, and
- wherein the high-speed bus comprises a plurality of lanes, wherein, whenever sending data, the DPIC is configured to either (i) send produced data concurrently on a set of the lanes, or (ii) send dummy data concurrently on the set of the lanes, and wherein the DCIC is configured to correct errors in the received data responsive to detecting, at a given time, produced data on one of the lanes in the set and dummy data on another of the lanes in the set.
A method for data transfer in a Multi-Chip-Module (MCM), the method comprising:
- for a data producing IC (DPIC) and a data-consuming IC (DCIC) that are part of the MCM and are connected to one another through a high-speed bus having a fixed data rate, defining (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced data, and durations of the first time periods and the second time periods, are preset;
- and
- sending data from the DPIC to the DCIC over the high-speed bus having the fixed data rate by alternating between the first time periods and the second time periods.
Dependencies are inferred from the claim text.