Output circuit, display driver, and display device

An output circuit comprising:

• a positive polarity voltage signal supplying circuit configured to supply a positive polarity voltage signal having a voltage higher than a reference power source voltage to a first node or block supply of the positive polarity voltage signal to the first node;
• a negative polarity voltage signal supplying circuit configured to supply a negative polarity voltage signal having a voltage lower than the reference power source voltage to a second node or block supply of the negative polarity voltage signal to the second node;
• a first output terminal;
• a first switch configured to connect the first output terminal and the first node at the time of an on state and block connection between the first output terminal and the first node at the time of an off state;
• a second switch configured to connect the first output terminal and the second node at the time of an on state and block connection between the first output terminal and the second node at the time of an off state;
• a third switch configured to apply the reference power source voltage to the first node at the time of an on state and stop application of the reference power source voltage to the first node at the time of an off state;
• a fourth switch configured to apply the reference power source voltage to the second node at the time of an on state and stop application of the reference power source voltage to the second node at the time of an off state;
• a first voltage control circuit configured to perform on/off control of the first switch;
• and
• a second voltage control circuit configured to perform on/off control of the second switch,
• wherein the first switch is configured using a P channel transistor of which a source is connected to the first node and a drain is connected to the first output terminal,
• wherein the second switch is configured using an N channel transistor of which a source is connected to the second node and a drain is connected to the first output terminal,
• wherein the first voltage control circuit has a first control means for changing a gate voltage of the P channel transistor in accordance with a change in a voltage supplied to the first node when the P channel transistor is controlled in the on state, and
• wherein the second voltage control circuit has a second control means for changing a gate voltage of the N channel transistor in accordance with a change in a voltage supplied to the second node when the N channel transistor is controlled in the on state.