US 2021/0231584 A1Published application

Smart defect calibration system in semiconductor wafer manufacturing

AssigneeElite Semiconductor Inc.

InventorsIYUN LEU, RAY JENN TSAY

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Abstract

The present invention relates to a smart defect calibration, diagnosis, sampling system and the method thereof for manufacturing fab is provided. The intelligent defect diagnosis method comprises: receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system, wherein the analyzing step further contains the sub-steps: superposing the defect contour pattern and the design layout, performing CAA to identify a killer or non-killer defect based on the open or short failure probability, defects are classified as high, medium, low, or negligible risk defect based on the Killer Defect Index, defect signal parameters, selecting defect samples based on the defect classification data, selecting alarm defect and filtering false defect with pattern match with defect pattern library and frequent failure defect library, performing coordinate conversion and pattern match between image contour and design layout for coordinate correction, creating a CAA accuracy correction system and defect size calibration system by analyzing original defect size data and defect contour size from image analysis, evaluating the defect size using measurement uncertainty analysis with statistical analysis methods to reach the purposes of increasing CAA accuracy and Killer Defect identification rate.

Claims20

Dependent claims

A smart defect calibration system in semiconductor wafer manufacturing, which includes a storage apparatus, a wafer manufacturing set having a wafer manufacturing equipment, a wafer defect inspection tool and a data processing apparatus, the storage apparatus is used to store an integrated circuit design layout file including a plurality of circuit layout patterns, the wafer manufacturing set arranges the circuit layout patterns of the integrated circuit design layout files onto wafer, the wafer defect inspection tool scans the wafer to retrieve a defect scan and inspection data, the data processing apparatus converts the defect scan and inspection data into a defect text and image data file, characterized in that:

the data processing apparatus performs a coordinate conversion and coordinate deviation calibration with the integrated circuit design layout file and defect text and image file;
the data processing apparatus executes an overlapping procedure, the data processing apparatus retrieves sequentially a defect coordinate, a defect size and a defect area of a defect contour from the defect text and image data file, and overlaps the defect size and defect area onto a coordinate deviation calibration value at a coordinate deviation area of the circuit layout pattern based on the corresponding defect coordinate after executing the coordinate conversion and coordinate deviation calibration;
the data processing apparatus executes a Critical Area Analysis (CAA), based on the overlapping of the calibrated defect size and defect area onto the mapped circuit layout pattern, the data processing apparatus uses the CAA to analyze a critical area within the coordinate deviation area for each of the defects, and decides a Killer Defect Index (KDI) value;
the data processing apparatus classifies each of the defects based on the KDI value of each defect and a defect intensity value of the defect contour, the classification of the defect includes a Dummy pattern defect, a No risk defect or a Killer defect;
and
the data processing apparatus executing a defect sample selection based on defect classification result.

3 more elements

the data processing apparatus performs a coordinate conversion and a coordinate deviation calibration with the integrated circuit design layout file and defect text and image file, the defect contour can be corrected after adjusting a defect size unit, a circuit layout pattern unit, and a mask unit to be the same dimension unit;
the data processing apparatus executes an overlapping procedure, the data processing apparatus retrieves sequentially a defect coordinate, a defect size and a defect area of a defect contour from the defect text and image data file, and overlaps the defect size and defect area onto a coordinate deviation calibration value at a coordinate deviation area of the circuit layout pattern based on the corresponding defect coordinate after executing the coordinate conversion and the coordinate deviation calibration;
the data processing apparatus executes a Critical Area Analysis (CAA), based on the overlapping of the calibrated defect size and defect area onto the mapped circuit layout pattern, the data processing apparatus uses the CAA to analyze a critical area within the coordinate deviation area for each of the defects, and decides a Killer Defect Index (KDI) value;
the data processing apparatus classifies each of the defects based on the KDI value of each defect and a defect intensity value of the defect contour, the classification of the defect includes a Dummy pattern defect, a No risk defect or a Killer defect;
and
the data processing apparatus executes a defect sample selection based on defect classification result.

3 more elements

the data processing apparatus executes an overlapping procedure, the data processing apparatus retrieves sequentially a defect coordinate, a defect size and a defect area of a defect contour from the defect text and image data file, and overlaps the defect size and defect area onto a coordinate deviation calibration value at a coordinate deviation area of the circuit layout pattern based on the corresponding defect coordinate after executing the coordinate conversion and coordinate deviation calibration;
the data processing apparatus checks whether there is the overlap of the defect contour between two circuit layout patterns and whether there is intersect of the defect contour with one of the circuit layout pattern, and judges whether the defect size and defect area are open circuit failure type or short circuit failure type, thereby a Killer Defect Index (KDI) value is decided;
the data processing apparatus classifies each of the defects based on the KDI value, a defect signal parameter, pattern match between the defect and the defect pattern library, and pattern match between the defect and the frequent failure defect library, the classification of the defect includes a Dummy pattern defect, a No risk defect or a Killer defect;
and
the data processing apparatus executes a defect sample selection based on defect classification result.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/233,349Filed 16 Apr 2021
Priority: 18 Sep 2017
Published: 29 Jul 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G01N 21/9501
Characterised by the material or shape of the object to be examined: semiconductor wafers
G01N 21/8851
Investigating the presence of flaws or contamination: scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment,…
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…

Family

Application62/559,784Continuation · filed 18 Sep 2017
Application16/134,114Continuation · filed 18 Sep 2018
Application17/233,349Continuation
US 11,016,035 B2Related patent
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US 2019/0086340 A1Published application
US 2021/0231584 A1This patent

From the US filing history. Foreign family members aren’t listed.