Semiconductor device with first-in-first-out circuit
AssigneeMicron Technology, Inc.
InventorsSeiji Narui, Yuki Ebihara
Life of this patent
Estimating the term…
Abstract
Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.
Claims20
An apparatus comprising:
- a first plurality of latches coupled in series and configured to receive an input signal, the first plurality of latches including a first latch configured to provide a first signal responsive, at least in part, to the input signal at a first timing;
- a second plurality of latches coupled in series and configured to receive the input signal, the second plurality of latches including a second latch configured to provide a second signal responsive, at least in part, to the input signal at a second timing that is different from the first timing;
- a first circuit configured to receive the first signal and provide the first signal at a third timing;
- and
- a second circuit configured to receive the second signal and provide the second signal at a fourth timing that is different from the third timing.
An apparatus comprising:
- a plurality of FIFO circuits configured to receive a plurality of corresponding bits of data, a first input pointer signal and a second input pointer signal, and further configured to provide the plurality of corresponding bits of data responsive, at least in part, to the first input pointer signal and the second input pointer signal,
- wherein each FIFO circuit of the plurality of FIFO circuits includes:
- a first latch configured to receive a corresponding bit of the data and the first input pointer signal, and further configured to provide the corresponding bit of the data responsive to the first input pointer signal;
- and
- a second latch configured to receive the corresponding bit of the data and the second input pointer signal, and further configured to provide the corresponding bit of the data responsive to the second input pointer signal.
An apparatus comprising:
- a data circuit configured to receive a string of input data including first input data, second input data following the first input data, and third input data following the second input data, the data circuit including:
- a first circuit including:
- a first plurality of first latch circuits configured to provide the first input data at a first timing;
- and
- a first plurality of second latch circuits configured to provide a first latched data responsive, at least in part, to the first input data at a second timing after the first timing;
- and
- a second circuit including:
- a second plurality of first latch circuits configured to provide the second input data at a third timing between the first timing and the second timing;
- and
- a second plurality of second latch circuits configured to provide a second latched data responsive, at least in part, to the second input data at a fourth timing after the second timing.
Dependencies are inferred from the claim text.