Second-order delta-sigma modulator, radio, and signal processing method performed by second-order delta-sigma modulator

A signal processing method performed by a second-order ΔΣ modulator, the second-order ΔΣ modulator comprising a two-stage integrator, a first arithmetic operation circuit, and a second arithmetic operation circuit, the two-stage integrator comprising a plurality of adder arrays that comprise first to fourth adder arrays, each of which comprises a plurality of adders, the method comprising:

• feeding back an output of a last stage of the second adder array as an input of a first stage of the first adder array;
• feeding back an output of a last stage of the fourth adder as an input of a first stage of the third adder array;
• inputting a sum bit string obtained in the first adder array to the third adder array;
• inputting a sum bit string obtained in the second adder array to the fourth adder array;
• performing an arithmetic operation based on inputs supplied to the plurality of adders of the first adder array to input an arithmetic operation result to the second adder array, by the first arithmetic operation circuit;
• and
• performing an arithmetic operation based on the inputs supplied to the plurality of adders of the first adder array and inputs supplied to the plurality of adders of the third adder array to input an arithmetic operation result to the fourth adder array, by the second arithmetic operation circuit.