Systems and methods for efficient matrix multiplication
AssigneeRain Neuromorphics Inc.
InventorJack David Kendall
Life of this patent
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Abstract
Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.
Claims14
A system of sparse vector-matrix multiplication comprising:
- a circuit layer;
- a plurality of electrodes formed on the circuit layer;
- and
- a plurality of non-volatile memory devices on and sparsely coupled with the plurality of electrodes, each of the plurality of non-volatile memory devices including a conductive core and a non-volatile memory material shell the conductive core having an axis and sides, the non-volatile memory material shell covering at least a portion of the sides of the conductive core, the plurality of non-volatile memory devices configured such that a portion of the non-volatile memory material shell resides between the conductive core of each of the plurality of non-volatile memory devices and the plurality of electrodes, wherein the circuit layer is configured to:
- receive a first plurality of input signals;
- write a second plurality of input signals on an input set of the plurality of electrodes;
- read from an output set of the plurality of electrodes a first plurality of output signals, and
- output a second plurality of output signals.
A method of providing a sparse vector-matrix multiplication device, comprising:
- providing a circuit layer;
- providing a plurality of electrodes on the circuit layer;
- and
- providing a plurality of non-volatile memory devices on and sparsely coupled with the plurality of electrodes, each of the plurality of non-volatile memory devices including a conductive core and a non-volatile memory material shell the conductive core having an axis and sides, the non-volatile memory material shell covering at least a portion of the sides of the conductive core, the plurality of non-volatile memory devices configured such that a portion of the non-volatile memory material shell resides between the conductive core of each of the plurality of non-volatile memory devices and the plurality of electrodes, wherein the circuit layer is configured to:
- receive a first plurality of input signals;
- write a second plurality of input signals on an input set of the plurality of electrodes;
- read from an output set of the plurality of electrodes a first plurality of output signals, and
- output a second plurality of output signals.
A method of performing a sparse vector-matrix multiplication comprising:
- receiving at an input set of a plurality of electrodes a plurality of input signals from a circuit layer, the plurality of electrodes being sparsely connected to a plurality of non-volatile memory devices on the plurality of electrodes, each of the plurality of non-volatile memory devices including a conductive core and a non-volatile memory material shell the conductive core having an axis and sides, the non-volatile memory material shell covering at least a portion of the sides of the conductive core, the plurality of non-volatile memory devices configured such that a portion of the non-volatile memory material shell resides between the conductive core of each of the plurality of non-volatile memory devices and the plurality of electrodes;
- and
- reading from an output set of the plurality of electrodes a plurality of output signals.
Dependencies are inferred from the claim text.