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US 2021/0202718 A1Published application
Fin-type field effect transistor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun Hsiung Tsai, Kei-Wei Chen
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Abstract
A fin-type field effect transistor including a substrate, insulators, a gate stack, a first spacer, a second spacer, and a third spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The first spacer is located over the sidewall of the gate stack. The second spacer is located over the first spacer. The first spacer and the second spacer includes carbon. The third spacer is located between the first spacer and the second spacer.
Claims20
A fin-type field effect transistor, comprising:
- a substrate having a plurality of fins;
- a plurality of insulators, located over the substrate and between the fins;
- a gate stack, located over the fins and on the insulators;
- a first spacer, located over a sidewall of the gate stack;
- a second spacer, located over the first spacer, wherein the first spacer and the second spacer comprise carbon;
- a third spacer, located between the first spacer and the second spacer;
- and
- wherein a first surface of the first spacer and a first surface of the second spacer are substantially coplanar to each other and are further substantially levelled with a surface of the gate stack, and the surface of the gate stack is in contact with the plurality of insulators, and
- wherein a second surface of the first spacer and a second surface of the second spacer are substantially coplanar to each other, the second surface of the first spacer is opposite to the first surface of the first spacer, and the second surface of the second spacer is opposite to the first surface of the second spacer.
6 more elements
A fin-type field effect transistor, comprising:
- a substrate having a plurality of fins;
- a plurality of insulators, located over the substrate and between the fins;
- a gate stack, located over the fins and on the insulators;
- a first spacer, located over a sidewall of the gate stack, wherein a material of the first spacer comprises SiCN;
- a second spacer, located over the first spacer;
- a third spacer, located over the second spacer, wherein a material of the third spacer comprises SiCN;
- a fourth spacer, located over the third spacer;
- and
- source/drain regions, located on opposite sides of the gate stack, the source/drain regions each having a sidewall in contact with and extending over a portion of a sidewall of the third spacer and coplanar with a sidewall of the fourth spacer at the sidewall of the third spacer,
- wherein a surface of the first spacer and a surface of the third spacer are substantially coplanar to each other and are further substantially levelled with a surface of the gate stack, and the surface of the gate stack is in contact with the plurality of insulators, and
- wherein the sidewall of the third spacer is connected to the surface of the third spacer, and an extending direction of the sidewall of the third spacer is perpendicular to an extending direction of the surface of the third spacer.
8 more elements
A fin-type field effect transistor, comprising:
- a substrate having a plurality of fins;
- a plurality of insulators, located over the substrate and between the fins;
- a gate stack, located over the fins and on the insulators;
- a multi-layered spacer, located over a sidewall of the gate stack;
- source/drain regions, located on opposite sides of the gate stack;
- and
- a first spacer, located over the multi-layered spacer and landed on the top surfaces of the source/drain regions, wherein the source/drain regions each have a sidewall in contact with and extending over a portion of a sidewall of the multi-layered spacer and coplanar with a sidewall of the first spacer at the sidewall of the multi-layered spacer;
- and
- an inter-layer dielectric layer, located on the top surfaces of the source/drain regions and spaced apart from the first spacer, the multi-layered spacer and the gate stack, wherein a top surface of the inter-layer dielectric layer is substantially levelled with a top surface of the gate stack facing away from the plurality of insulators, and the first spacer is located between the inter-layer dielectric layer and the multi-layered spacer.
6 more elements
Dependencies are inferred from the claim text.