Electronic device and method of manufacturing the same
AssigneeSK hynix Inc.
InventorSi Jung YOO
Life of this patent
Estimating the term…
Abstract
A semiconductor memory may include: variable resistance layers and insulating layers alternately stacked; conductive pillars passing through the variable resistance layers and the insulating layers; a slit insulating layer passing through the insulating layers and extending in a first direction; and conductive layers interposed between the slit insulating layer and the variable resistance layers. The variable resistance layers may remain in an amorphous state during a program operation.
Claims15
An electronic device comprising a semiconductor memory, the semiconductor memory comprising:
- variable resistance layers and insulating layers alternately stacked;
- conductive pillars passing through the variable resistance layers and the insulating layers;
- a slit insulating layer passing through the insulating layers and extending in a first direction;
- and
- conductive layers interposed between the slit insulating layer and the variable resistance layers,
- wherein the variable resistance layers remain in an amorphous state during a program operation.
An electronic device comprising a semiconductor memory, the semiconductor memory comprising:
- insulating layers stacked;
- first variable resistance layers alternately stacked with the insulating layers and each extending in a first direction;
- vertical bit lines passing through the first variable resistance layers and the insulating layers;
- a first slit insulating layer passing through the insulating layers and extending in the first direction;
- a second slit insulating layer passing through the insulating layers and extending in the first direction;
- first word lines each interposed between the first slit insulating layer and each of the first variable resistance layers;
- and
- second word lines each interposed between the second slit insulating layer and each of the first variable resistance layers,
- wherein first memory cells are respectively disposed between the vertical bit lines and the first word lines, second memory cells are respectively disposed between the vertical bit lines and the second word lines, and each of the first memory cells and each of the second memory cells are disposed adjacent in a second direction and share a corresponding one of the first variable resistance layers.
Dependencies are inferred from the claim text.