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US 2021/0202575 A1Published application
Circuit and method to enhance efficiency of memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHUNG-CHANG YU
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Abstract
A method includes: providing a modulation circuit, determined an operation mode of a memory array, providing a first voltage corresponding to a positive temperature coefficient in response to a read operation of the memory array, and providing a second voltage corresponding to a negative temperature coefficient in response to a write operation of the memory array. The modulation circuit is configured to generate a temperature-dependent voltage and provide the same to the memory array.
Claims20
A method, comprising:
- providing a modulation circuit, the modulation circuit configured to generate a temperature-dependent voltage and provide the same to a memory array;
- determined an operation mode of the memory array;
- providing a first voltage corresponding to a positive temperature coefficient in response to a read operation of the memory array;
- and
- providing a second voltage corresponding to a negative temperature coefficient in response to a write operation of the memory array.
2 more elements
A method, comprising:
- providing a modulation circuit and a driving circuit, the modulation circuit configured to generate a temperature-dependent voltage and provide the same to the driving circuit;
- determined an operation mode of a memory array;
- providing a first voltage corresponding to a positive temperature coefficient in response to a read operation of the memory array;
- providing a second voltage corresponding to a negative temperature coefficient in response to a write operation of the memory array;
- providing a first driving current in response to the first voltage corresponding to the positive temperature coefficient to the memory array during the read operation;
- and
- providing a second driving current in response to the second voltage corresponding to the negative temperature coefficient to the memory array during the write operation.
4 more elements
A method, comprising:
- providing a first portion of a circuit, the first portion configured for generating a first current, the first current comprising a first branch current and a second branch current, the first branch current having a first magnitude, the second branch current having a second magnitude, a first resistive element receiving the first branch current, a second resistive element receiving the second branch current, the second resistive element being an adjustable resistive element;
- providing a second portion of the circuit, the second portion connected to the first portion, and configured for generating a second current, the second current having the same magnitude as the first current, the second current comprising a first branch current and a second branch current, the first branch current having the first magnitude, the second branch current having the second magnitude, a third resistive element receiving the second branch current of the second current, the third resistive element being an adjustable resistive element;
- and
- providing an output stage of the circuit, the output stage connected to the second portion and the first portion, and configured for generating a third current and an output voltage, the third current having the same magnitude as the first current, the output voltage having a first voltage and a second voltage, the first voltage corresponding to a positive temperature coefficient and corresponding to the first magnitude, the second voltage corresponding to a negative temperature coefficient and corresponding to the second magnitude, a fourth resistive element receiving the third current, the fourth resistive element being an adjustable resistive element.
1 more element
Dependencies are inferred from the claim text.