Cfet sram bit cell with three stacked device decks

A static random access memory (SRAM), comprising:

• a plurality of SRAM bit cells on a substrate, each SRAM bit cell comprising:
• at least six transistors including at least two NMOS transistors and at least two PMOS transistors;
• each of the six transistors being lateral gate-all-around transistors in that gates wraps all around a cross section of channels of the at least six transistors;
• the at least six transistors positioned in three decks in which a third deck is positioned vertically above a second deck, and the second deck is positioned vertically above a first deck relative to a working surface of the substrate;
• a first inverter formed using a first transistor positioned in the second deck and a second transistor positioned in the third deck;
• a second inverter formed using a third transistor positioned in the second deck and a fourth transistor positioned in the third deck;
• and
• a pass gate located in the first deck.

A method for forming a static random access memory (SRAM) bit cell on a substrate, the method comprising:

• forming at least six transistors including at least two NMOS transistors and at least two PMOS transistors, each of the six transistors being lateral gate-all-around transistors in that gates wraps all around a cross section of channels of the at least six transistors, the at least six transistors positioned in three decks in which a third deck is positioned vertically above a second deck, and the second deck is positioned vertically above a first deck relative to a working surface of the substrate;
• forming a first inverter formed using a first transistor positioned in the second deck and a second transistor positioned in the third deck;
• forming a second inverter formed using a third transistor positioned in the second deck and a fourth transistor positioned in the third deck;
• and
• forming a pass gate located in the first deck.