Memory device and manufacturing method thereof

A method for manufacturing a memory device, comprising:

• forming a writing transistor and a reading transistor over a substrate;
• forming a memory cell over the substrate, comprising:
• forming a tunneling layer over the substrate;
• forming a blanket dielectric layer over the tunneling layer and the substrate;
• etching the blanket dielectric layer to form a storage layer on the tunneling layer;
• forming a first electrode over the tunneling layer;
• and
• forming a second electrode on the tunneling layer and adjacent the storage layer;
• and
• forming an inter-metal dielectric layer over the writing transistor, the reading transistor, and the memory cell to interconnect the writing transistor, the reading transistor, and the memory cell.

A method comprising:

• forming source/drain regions in a transistor region of a substrate;
• forming a first interfacial layer over the transistor region and between the source/drain regions and a second interfacial layer over a memory region of the substrate after forming the source/drain regions;
• forming a gate dielectric layer over the first interfacial layer and a storage layer over the second interfacial layer such that the storage layer exposes a portion of the second interfacial layer;
• forming a gate electrode over the gate dielectric layer, a first electrode over the storage layer, and a second electrode over the portion of the second interfacial layer such that the second interfacial layer laterally surrounds the second electrode;
• and
• forming an inter-metal dielectric layer over the substrate to interconnect the source/drain regions, the gate electrode, the first electrode, and the second electrode.

A method comprising:

• forming a nanowire over a substrate;
• subsequently and conformally forming an interfacial film, a dielectric film, and a conductive film over the nanowire;
• removing portions of the interfacial film, the dielectric film, and the conductive film to expose a top surface of the nanowire;
• forming a tunneling layer over the top surface of the nanowire;
• forming a first spacer to cover the tunneling layer and remaining portions of the interfacial film, the dielectric film, and the conductive film;
• forming an opening in the first spacer to expose the tunneling layer;
• and
• forming an electrode in the opening and over the tunneling layer.