Memory cell array and method of manufacturing same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShih-Lien Linus LU
Life of this patent
Estimating the term…
Abstract
A memory cell array includes a first and second memory cell, a first and second word line and a first bit line. The first memory cell is in a first row in a first direction. The second memory cell is in a second row in the first direction, and is separated from the first memory cell in a second direction. The first word line extends in the first direction and is coupled to the first memory cell. The second word line extends in the first direction and is coupled to the second memory cell. The first bit line extends in the second direction and is coupled to the first and second memory cell. The first memory cell corresponds to a five transistor memory cell. The first memory cell includes a first active region having a first length, and a second active region having a second length.
Claims20
A method of forming a memory cell array, the method comprising:
- generating a first set of tiles extending in a first direction, wherein the generating the first set of tiles comprises:
- generating a first layout design of a first set of memory cells, each tile of the first set of tiles corresponds to the first layout design of the first set of memory cells, each tile of the first set of tiles is offset from an adjacent tile of the first set of tiles in a second direction different from the first direction, and each tile of the first set of tiles includes at least a first corner notch;
- generating a second set of tiles extending in the first direction, wherein the generating the second set of tiles comprises:
- generating a second layout design of a second set of memory cells, each tile of the second set of tiles corresponds to the second layout design of the second set of memory cells, each tile of the second set of tiles is offset from an adjacent tile of the second set of tiles in the second direction, and each tile of the second set of tiles includes at least a second corner notch,
- wherein each first corner notch is flush with each second corner notch, each tile of the first set of tiles extends in a third direction different from the first direction and the second direction, the first set of tiles and the second set of tiles alternate with each other in the second direction, and each tile of the second set of tiles extends in the third direction, and at least one of the above generating operations is performed by a hardware processor, and the first layout design is stored in a non-transitory computer-readable medium;
- and
- manufacturing the memory cell array based on at least the first layout design.
A method of forming a memory cell array having a first set of memory cells, the method comprising:
- generating, by a processor, a layout design of the memory cell array, the layout design corresponding to a tile having a first corner notch and a second corner notch, wherein the generating of the layout design comprises:
- generating a first active region layout pattern corresponding to fabricating a first active region of the memory cell array, the first active region layout pattern extending between the first corner notch and the second corner notch, and being adjacent to a first side of a memory cell of the first set of memory cells;
- and
- generating a second active region layout pattern corresponding to fabricating a second active region of the memory cell array, the second active region layout pattern being adjacent to a second side of the memory cell opposite from the first side of the memory cell, the second active region layout pattern being separated from the first active region layout pattern in a first direction, the first active region layout pattern and the second active region layout pattern extending in a second direction and being located on a first layout level;
- wherein at least one of the above layout patterns is stored in a non-transitory computer-readable medium, and at least one of the above generating operations is performed by a hardware processor;
- and
- manufacturing the memory cell array based on the layout design.
A memory cell array comprising:
- a first memory cell arranged in a first row in a first direction;
- a second memory cell arranged in a second row in the first direction, and being separated from the first memory cell in a second direction different from the first direction;
- a first word line extending in the first direction, and being coupled to the first memory cell;
- a second word line extending in the first direction, and being coupled to the second memory cell;
- and
- a first bit line extending in the second direction, and being coupled to the first memory cell and the second memory cell;
- wherein the first memory cell corresponds to a five transistor (5T) memory cell, and the first memory cell comprises:
- a first active region having a first length in the second direction;
- and
- a second active region having a second length in the second direction and being different from the first length, the first active region and the second active region extending in the second direction, being located on a first level and being separated from each other in the first direction.
Dependencies are inferred from the claim text.