Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorJongyoun KIM
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a semiconductor chip, a redistribution insulating layer having a first opening, and an external connection bump including a first portion filling the first opening. A lower bump pad includes a first surface and a second surface opposite the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a cover portion surrounding side surfaces of the contact portion. A first conductive barrier layer surrounds side surfaces of the lower bump pad and is disposed between the lower bump pad and the redistribution insulating layer. A redistribution pattern directly contacts the second surface of the lower bump pad and is configured to electrically connect the lower bump pad to the semiconductor chip.
Claims20
A semiconductor package comprising:
- a semiconductor chip;
- a redistribution insulating layer having a first opening;
- an external connection bump including a first portion filling the first opening;
- a lower bump pad including a first surface and a second surface opposite the first surface, the first surface including a contact portion that directly contacts the first portion of the external connection bump and a cover portion surrounding side surfaces of the contact portion;
- a first conductive barrier layer surrounding side surfaces of the lower bump pad and disposed between the lower bump pad and the redistribution insulating layer;
- and
- a redistribution pattern directly contacting the second surface of the lower bump pad and configured to electrically connect the lower bump pad to the semiconductor chip.
A semiconductor package comprising:
- a semiconductor chip;
- a redistribution insulating layer including an opening;
- an external connection bump including a first portion filling the opening;
- a lower bump pad including a first surface and a second surface opposite the first surface, the first surface including a contact portion that directly contacts the first portion of the external connection bump and a cover portion surrounding side surfaces of the contact portion and is covered with the redistribution insulating layer;
- a first conductive barrier layer surrounding side surfaces of the lower bump pad and disposed between a side surface of the lower bump pad and the redistribution insulating layer in a horizontal direction;
- and
- a second conductive barrier layer disposed on the cover portion of the lower bump pad and surrounding a side wall of the external connection bump,
- wherein a surface of the external connection bump contacting the contact portion of the lower bump pad is coplanar in a vertical direction with a surface of the second conductive barrier layer that directly contacts the cover portion of the lower bump pad, the vertical direction is perpendicular to the horizontal direction.
A semiconductor package comprising:
- a semiconductor chip;
- a redistribution insulating layer including an opening;
- an external connection bump including a first portion filling the opening;
- a lower bump pad including a first conductive layer that directly contacts a first portion of the external connection bump, a diffusion barrier layer disposed on the first conductive layer, and a second conductive layer disposed on the diffusion barrier layer and spaced apart from the first conductive layer in a vertical direction;
- and
- a first conductive barrier layer surrounding side surfaces of the lower bump pad and disposed between the lower bump pad and the redistribution insulating layer in a horizontal direction that is perpendicular to the vertical direction.
Dependencies are inferred from the claim text.