Structure and Method for Transistors Having Backside Power Rails

A semiconductor structure, comprising:

• a substrate having a front side and a back side;
• a fin active region protruded out from the front side of the substrate;
• a gate stack disposed on the fin active region;
• a source feature and a drain feature formed on the active region and interposed by the gate stack;
• a front contact feature landing on the drain feature from the front side of the substrate;
• a backside power rail formed on the back side of the substrate;
• and
• a backside contact feature interposed between the backside power rail and the source feature, wherein the backside contact feature electrically connects the backside power rail to the source feature, wherein
• the backside contact feature includes a first silicide layer disposed on the back side and in direct contact with the source feature, and
• the front contact feature includes a second silicide layer disposed on the front side and in direct contact with the drain feature.

A method of forming an integrated circuit structure, comprising:

• receiving a substrate having a front surface and a back surface;
• forming a shallow trench isolation (STI) feature in the front surface of the substrate, thereby defining a fin active region surrounded by the STI feature;
• forming a gate stack on the fin-type active regions;
• forming a source feature and a drain feature on the fin active regions, wherein the gate stack spans from the source feature to the drain feature;
• forming an interconnect structure on the gate stack, the source feature and the drain feature from the front surface, wherein the interconnect structure includes a front contact feature contacting the drain feature;
• thinning down the substrate from the back surface such that source feature is exposed with an exposed surface;
• forming a backside contact feature landing on the exposed surface of the source feature;
• and
• forming a backside power rail landing on the backside contact feature.