Parallel plate capacitor resistance modeling and extraction

A system comprising:

• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
• access a description of a parallel plate capacitor structure in an integrated circuit, the parallel plate capacitor structure comprising a first plate and a second plate, wherein each plate is connected to an interconnect structure at a plurality of connection points;
• identify an overlap region of the two plates, wherein the overlap region of the two plates forms a parallel plate capacitor and the first plate has no connection points within the overlap region;
• and
• determining, by a processor, a lumped element model for resistance of the overlap region of the first plate, the lumped element model comprising edge nodes of the overlap region, a capacitor node for a lumped capacitance of the parallel plate capacitor, and lumped resistances between the edge nodes and the capacitor node.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• access a description of a parallel plate capacitor structure in an integrated circuit, the parallel plate capacitor structure comprising a first plate and a second plate, wherein each plate is connected to an interconnect structure at a plurality of connection points;
• identify an overlap region of the two plates, wherein the overlap region of the two plates forms a parallel plate capacitor and the first plate has no connection points within the overlap region;
• and
• determining, by a processor, a lumped element model for resistance of the overlap region of the first plate, the lumped element model comprising edge nodes of the overlap region, a capacitor node for a lumped capacitance of the parallel plate capacitor, and lumped resistances between the edge nodes and the capacitor node.