Memory-based processors
AssigneeNeuroBlade Ltd.
InventorsElad SITY, Eliad HILLEL
Life of this patent
Estimating the term…
Abstract
A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.
Claims35
1-30. (canceled)
A method for producing selectable sized memory chips from a wafer, comprising:
- forming a wafer comprising a group of dies and a coupling circuit, wherein the dies of the group comprise memory units, and wherein the coupling circuit is coupled to the dies of the group;
- forming the selectable sized memory chips by at least one of:
- cutting a region of the wafer that comprises the group of dies and the coupling circuit, to provide a single memory chip that comprises the group of dies;
- and
- configuring at least one controller associated with the group of dies, to control the group of dies together as a single memory chip;
- and cutting regions of the wafer, each region of the wafer including a die of the group to provide a plurality of separate memory chips.
A method for producing selectable sized memory chips from a wafer, comprising:
- forming a plurality of memory chips on the wafer, the plurality of memory chips arranged along one or more rows;
- forming at least one shared input-output bus corresponding to the one or more rows, wherein the at least one shared input-output bus electrically connects at least two of the plurality of memory chips to function together as a single chip;
- and
- cutting at least two of the plurality of memory chips off the wafer with at least one corresponding portion of the shared input-output bus such that at least one memory controller is configurable to control the at least two of the plurality of memory chips to function together as a single chip.
A wafer for providing selectable sized memory chips comprising:
- a group of dies, wherein the dies of the group comprise memory units;
- and
- at least one input-output bus shared by the group of dies, wherein the dies of the group are arranged to allow for a plurality of cutting shapes each corresponding to a memory chip to be produced and each of the plurality of cutting shapes excluding at least a portion of the shared input-output bus.
A wafer for providing selectable sized memory chips comprising:
- a group of dies, wherein the dies of the group comprise memory units;
- a coupling circuit, wherein the coupling circuit is coupled to the dies of the group;
- and
- wherein the dies of the group are arranged to allow for a plurality of cutting shapes each corresponding to a memory chip to be produced and each of the plurality of cutting shapes excluding at least a portion of the coupling circuit.
64-225. (canceled)
Dependencies are inferred from the claim text.