Back to results
US 2021/0202025 A1Published application
Memory-based processors
AssigneeNeuroBlade Ltd.
InventorsElad SITY, Eliad HILLEL
Life of this patent
Estimating the term…
Abstract
A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.
Claims41
1-82. (canceled)
An integrated circuit that comprises:
- a memory unit comprising memory cells, an output port, and read circuitry;
- and
- a processing unit;
- wherein the read circuitry comprises a reduction unit and a first group of in-memory read paths for outputting up to a first number of bits through the output port;
- wherein the processing unit is configured to send to the memory unit a read request for reading a second number of bits from the memory unit;
- and
- wherein the reduction unit is configured to control the in-memory read paths, during a read operation triggered by the read request, based on the first number of bits and the second number of bits.
4 more elements
A method for energy reduction of an integrated circuit, the method comprises:
- sending, by a processing unit of the integrated circuit and to a memory unit of the integrated circuit, a read request for reading a second number of bits from the memory unit;
- wherein the memory unit comprises memory cells, an output port, and read circuitry that comprises a reduction unit and a first group of in-memory read paths for outputting up to a first number of bits through the output port;
- and
- controlling, by the reduction unit, the in-memory read paths, during a read operation triggered by the read request, based on the first number of bits and the second number of bits.
1 more element
An integrated circuit that comprises:
- a memory unit comprising memory cells, an output port, and write circuitry;
- and
- a processing unit;
- wherein the write circuitry comprises a reduction unit and a first group of in-memory write paths for outputting up to a first number of bits through the output port;
- wherein the processing unit is configured to send to the memory unit a write request for writing a second number of bits from the memory unit;
- and
- wherein the reduction unit is configured to control the in-memory write paths, during a write operation triggered by the write request, based on the first number of bits and the second number of bits.
4 more elements
122-225. (canceled)
Dependencies are inferred from the claim text.