Multi-state programming of memory cells

A method of operating memory, comprising:

• programming a memory cell to one of at least three possible data states by:
• applying a voltage pulse to the memory cell;
• determining the memory cell snaps back in response to the applied voltage pulse;
• turning off a current to the memory cell upon determining the memory cell snaps back;
• and
• applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.

An apparatus, comprising:

• a memory having a plurality of memory cells;
• and
• circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by:
• applying a voltage pulse to the memory cell;
• determining the memory cell snaps back in response to the applied voltage pulse;
• turning off a current to the memory cell upon determining the memory cell snaps back;
• and
• applying a single additional voltage pulse having a first polarity or a single additional voltage pulse having a second polarity that is opposite the first polarity to the memory cell after turning off the current to the memory cell.

A method of operating memory, comprising:

• programming a memory cell to one of four possible data states by:
• applying a voltage pulse to the memory cell;
• determining the memory cell snaps back in response to the applied voltage pulse;
• turning off a current to the memory cell upon determining the memory cell snaps back;
• and
• applying a first number of additional voltage pulses to the memory cell after turning off the current to the memory cell, wherein each of the first number of additional voltage pulses have a first polarity or each of the first number of additional voltage pulses have a second polarity that is opposite the first polarity;
• or
• applying a second number of additional voltage pulses to the memory cell after turning off the current to the memory cell, wherein each of the second number of additional voltage pulses have the first polarity or each of the second number of additional voltage pulses have the second polarity.

An apparatus, comprising:

• a memory having a plurality of memory cells;
• and
• circuitry configured to program a memory cell of the plurality of memory cells to one of six possible data states by:
• applying a voltage pulse to the memory cell;
• determining the memory cell snaps back in response to the applied voltage pulse;
• turning off a current to the memory cell upon determining the memory cell snaps back;
• and
• applying a first number of additional voltage pulses to the memory cell after turning off the current to the memory cell, wherein each of the first number of additional voltage pulses have a first polarity or each of the first number of additional voltage pulses have a second polarity that is opposite the first polarity;
• or
• applying a second number of additional voltage pulses to the memory cell after turning off the current to the memory cell, wherein each of the second number of additional voltage pulses have the first polarity or each of the second number of additional voltage pulses have the second polarity;
• or
• applying a third number of additional voltage pulses to the memory cell after turning off the current to the memory cell, wherein each of the third number of additional voltage pulses have the first polarity or each of the third number of additional voltage pulses have the second polarity.