Memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsBilal Ahmad JANJUA, Sung Whan SEO
Life of this patent
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Abstract
A memory device includes a charge pump connected to a power supply voltage and including a plurality of stages to output an output voltage, a stage counter configured to output a count value that incrementally increases to a number of the stages, and a regulator configured to compare the output voltage with a reference output voltage of the charge pump that is generated using the incrementally increasing count value obtained by the stage counter, and to output a pump operation signal at a time when the reference output voltage becomes greater than or equal to the output voltage, wherein the charge pump operates in response to the pump operation signal.
Claims20
A memory device comprising:
- a charge pump connected to a power supply voltage, the charge pump comprising a plurality of stages to output an output voltage;
- a stage counter configured to output a count value that incrementally increases to a number of the plurality of stages;
- and
- a regulator configured to compare the output voltage with a reference output voltage of the charge pump, the reference output voltage being generated using the incrementally increasing count value obtained by the stage counter, and to output a pump operation signal at a time when the reference output voltage becomes greater than or equal to the output voltage,
- wherein the charge pump is configured to operate in response to the pump operation signal.
A memory device comprising:
- a charge pump connected to a power supply voltage, the charge pump comprising a plurality of stages;
- a stage counter configured to output a respective stage reference signal corresponding to each stage from among the plurality of stages;
- and
- a regulator configured to generate a stage operation signal different from the stage reference signal based on the stage reference signal and a first stage control signal,
- wherein the regulator is configured to output the stage operation signal when the first stage control signal is at a first logic level,
- wherein the regulator is configured to output the stage reference signal when the first stage control signal is at a second logic level, and
- wherein the charge pump is configured to generate an output voltage using a number of stages corresponding to the stage reference signal or the stage operation signal output by the regulator.
A memory device comprising:
- a memory cell array comprising a plurality of memory cells;
- and
- a voltage generator configured to generate a program voltage of a memory cell in the memory cell array using a power supply voltage,
- wherein the voltage generator comprises:
- a charge pump comprising a plurality of stages, the charge pump being configured to generate the program voltage using the power supply voltage, and
- a regulator configured to control an operation time point of the charge pump by comparing a reference output voltage of the charge pump, generated using at least one of the plurality of stages, with an output voltage of the charge pump as it recovers from the program voltage to a ground voltage after the charge pump generates the program voltage.
Dependencies are inferred from the claim text.