Apparatus and methods for rapid data destruction

An apparatus, comprising:

• a string of series-connected memory cells connected between a common source and a data line and comprising a plurality of principal memory cells and a plurality of dummy memory cells;
• a plurality of dummy access lines, each dummy access line of the plurality of dummy access lines connected to a control gate of a respective dummy memory cell of the plurality of dummy memory cells;
• a plurality of principal access lines, each principal access line of the plurality of principal access lines connected to a control gate of a respective principal memory cell of the plurality of principal memory cells;
• and
• a controller for access of the string of series-connected memory cells, wherein the controller is configured to cause the apparatus to:
• connect a particular dummy memory cell of the plurality of dummy memory cells to the common source and isolate the particular dummy memory cell from the data line;
• apply a first programming pulse to the control gate of the particular dummy memory cell sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level higher than a predetermined pass voltage to be received by the particular dummy memory cell during a read operation on the string of series-connected memory cells;
• isolate each principal memory cell of the plurality of principal memory cells from the common source and connect each principal memory cell of the plurality of memory cells to the data line;
• and
• concurrently apply a second programming pulse to a control gate of each principal memory cell of the plurality of principal memory cells sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.

An apparatus, comprising:

• a string of series-connected memory cells connected between a common source and a data line;
• a first plurality of access lines, each access line of the first plurality of access lines connected to a control gate of a respective memory cell of the string of series-connected memory cells configured for output of data using a read operation;
• a second plurality of access lines, each access line of the second plurality of access lines connected to a control gate of a respective memory cell of the string of series-connected memory cells configured to be inaccessible using a read operation;
• and
• a controller for access of the string of series-connected memory cells, wherein the controller is configured to cause the apparatus to:
• electrically float the first plurality of access lines and the second plurality of access lines;
• apply a first programming pulse to a while electrically floating remaining access lines of the second plurality of access lines and while electrically floating the first plurality of access lines;
• apply a second programming pulse to each access line of the first plurality of access lines while applying a pass voltage to each access line of the second plurality of access lines between any access line of the first plurality of access lines and an end of the string of series-connected memory cells opposite the particular access line;
• and
• concurrently erase the respective memory cell for the particular access line and the respective memory cell for each access line of the first plurality of access lines.