Semiconductor memory device and method of operating the same
AssigneeSK hynix Inc.
InventorHee Joo LEE
Life of this patent
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Abstract
A semiconductor memory device, and a method of operation, include: a memory block coupled with a plurality of word lines and a plurality of bit lines; a peripheral circuit configured to perform a program operation and a read operation on the memory block; and control logic configured to control the peripheral circuit such that a word line overdrive period overlaps with a bit line overdrive period in a bit line precharge operation during at least one of the program operation and the read operation.
Claims20
A semiconductor memory device comprising:
- a memory block coupled with a plurality of word lines and a plurality of bit lines;
- a peripheral circuit configured to perform a program operation and a read operation on the memory block;
- and
- control logic configured to control the peripheral circuit such that a word line overdrive period overlaps with a bit line overdrive period in a bit line precharge operation during at least one of the program operation and the read operation.
A semiconductor memory device comprising:
- a memory block coupled with a plurality of word lines and a plurality of bit lines;
- a peripheral circuit configured to apply a set voltage to each of the plurality of word lines and the plurality of bit lines;
- and
- control logic configured to control the peripheral circuit such that, during a bit line precharge operation, a word line overdrive period in which a first overdrive voltage is applied to a selected word line among the plurality of word lines partially overlaps with a bit line overdrive period in which a second overdrive voltage is applied to each of the plurality of bit lines.
A method of operating a semiconductor memory device, comprising:
- applying a first overdrive voltage to a selected word line during a word line overdrive period;
- applying a second overdrive voltage to each of multiple bit lines during a bit line overdrive period;
- applying a first target voltage to the selected word line after the word line overdrive period;
- and
- precharging the multiple bit lines to a second target voltage after the bit line overdrive period,
- wherein the word line overdrive period partially overlaps with the bit line overdrive period.
Dependencies are inferred from the claim text.