Managing sub-block erase operations in a memory sub-system

A system comprising:

• a memory device;
• and
• a processing device, operatively coupled with the memory device, to perform operations comprising:
• receiving an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising one or more select gate devices (SGDs) and a plurality of data storage devices;
• for each sub-block of the plurality of sub-blocks not selected for erase:
• applying an input voltage at a bitline of the respective sub-block;
• and
• applying a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines comprising one or more wordlines coupled to the one or more SGDs and one or more dummy wordlines coupled to a first subset of the plurality of data storage devices, wherein each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval, and wherein the input voltage is reduced to a threshold level at a first data wordline that is used for storing host data;
• and
• performing an erase operation to erase data stored at the selected sub-block.