US 2021/0202004 A1 · REDUNDANCY IN MICROELECTRONIC DEVICES, AND RELATED METHODS, DEVICES, AND SYSTEMS

Abstract

Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.

Claims20

Dependent claims

A method of operating a memory device, comprising:

comparing a selected column address for a first row section of a memory array to one or more of a number of column addresses for defective memory cells of the first row section;
and
accessing a redundant memory cell of a second row section of the memory array in response to the selected column address for the first row section matching a stored column address of the number of column addresses for defective memory cells of the first row section.

A system comprising:

at least one input device;
at least one output device;
at least one processor device operably coupled to the input device and the output device;
and
a memory device operably coupled to the at least one processor device and comprising:
a memory array including a number of row sections, each row section including a number of memory cells, the number of row sections including a row section pair including a first row section and a second row section;
and
control circuitry configured to activate the second row section and convey a redundant column select signal to the memory array to select a redundant memory cell of the second row section in response to a selected column address matching a column address of a first number of column addresses for a defective memory cells of the first row section.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/249,284Filed 25 Feb 2021

Priority

26 Dec 2019

Published

1 Jul 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
G11C 29/24
Address generation devices; Devices for accessing memories, e.g. details of addressing circuits: accessing extra cells, e.g. dummy cells or…

Redundancy in microelectronic devices, and related methods, devices, and systems

Life of this patent

Redundancy in microelectronic devices, and related methods, devices, and systems

Life of this patent

Abstract

Claims20