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US 2021/0202002 A1Published application
Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate
AssigneeToshiba Memory Corporation
InventorsTakatoshi MINAMOTO, Toshiki HISADA, Dai NAKAMURA
Life of this patent
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Abstract
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.
Claims15
A semiconductor memory device, comprising:
- a bit line;
- a source line;
- a memory cell unit including
- a first selection transistor connected to the bit line,
- a second selection transistor connected to the source line, and
- a plurality of memory cells connected in series between the first selection transistor and the second selection transistor, the memory cells including
- a first memory cell,
- a second memory cell located closer to the first selection transistor than the first memory cell,
- a third memory cell located closer to the first selection transistor than the second memory cell, and
- a fourth memory cell located closer to the first selection transistor than the third memory cell;
- a first word line connected to the first memory cell;
- a second word line connected to the second memory cell;
- a third word line connected to the third memory cell;
- a fourth word line connected to the fourth memory cell;
- a driver circuit configured to apply a voltage to
- the first word line,
- the second word line,
- the third word line, and
- the fourth word line;
- a first transistor including a first diffused layer connected to the first word line and a second diffused layer connected to the driver circuit;
- a second transistor connected between the second word line and the driver circuit;
- a third transistor connected between the third word line and the driver circuit;
- and
- a fourth transistor connected between the fourth word line and the driver circuit,
- wherein when data is written into the first memory cell,
- a first voltage is applied to the first word line,
- a second voltage is applied to the second word line,
- a third voltage is applied to the third word line, and
- a fourth voltage is applied to the fourth word line,
- wherein the first voltage is larger than the second voltage, the third voltage and the fourth voltage, the second voltage is larger than the third voltage, and the fourth voltage is larger than the third voltage,
- wherein the second word line, the third word line, and the fourth word line are not located above the first diffused layer and the second diffused layer, and
- wherein each of the first word line, the second word line, the third word line, and the fourth word line is arranged in a first direction,
- wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor has a gate length in a second direction perpendicular to the first direction,
- wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged in the first direction, and
- wherein a distance between the first transistor and the memory cell unit is smaller than a distance between the second transistor and the memory cell unit.
32 more elements
A method for controlling a semiconductor memory device, the semiconductor memory device comprising:
- a bit line;
- a source line;
- a memory cell unit including
- a first selection transistor connected to the bit line,
- a second selection transistor connected to the source line, and
- a plurality of memory cells connected in series between the first selection transistor and the second selection transistor, the memory cells including
- a first memory cell,
- a second memory cell located closer to the first selection transistor than the first memory cell,
- a third memory cell located closer to the first selection transistor than the second memory cell, and
- a fourth memory cell located closer to the first selection transistor than the third memory cell;
- a first word line connected to the first memory cell;
- a second word line connected to the second memory cell;
- a third word line connected to the third memory cell;
- a fourth word line connected to the fourth memory cell;
- a driver circuit configured to apply a voltage to
- the first word line,
- the second word line,
- the third word line, and
- the fourth word line;
- a first transistor including a first diffused layer connected to the first word line and a second diffused layer connected to the driver circuit;
- a second transistor connected between the second word line and the driver circuit;
- a third transistor connected between the third word line and the driver circuit;
- and
- a fourth transistor connected between the fourth word line and the driver circuit,
- wherein the second word line, the third word line, and the fourth word line are not located above the first diffused layer and the second diffused layer, and
- wherein each of the first word line, the second word line, the third word line, and the fourth word line is arranged in a first direction,
- wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor has a gate length in a second direction perpendicular to the first direction,
- wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged in the first direction, and
- wherein a distance between the first transistor and the memory cell unit is smaller than a distance between the second transistor and the memory cell unit,
- the method comprising:
- writing data into the first memory cell by, using the driver circuit,
- applying a first voltage to the first word line,
- applying a second voltage to the second word line,
- applying a third voltage to the third word line, and
- applying a fourth voltage to the fourth word line, and
- wherein the first voltage is larger than the second voltage, the third voltage and the fourth voltage, the second voltage is larger than the third voltage, and the fourth voltage is larger than the third voltage.
33 more elements
Dependencies are inferred from the claim text.