Three-state programming of memory cells
AssigneeMicron Technology, Inc.
InventorsHernan A. Castro, Jeremy M. Hirst, Shanky K. Jain, Richard K. Dodge, William A. Melton
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Abstract
The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.
Claims30
An apparatus, comprising:
- a memory having a plurality of memory cells;
- and
- circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by:
- applying a voltage pulse to the memory cell;
- determining whether the memory cell snaps back in response to the applied voltage pulse;
- and
- applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.
A method of operating memory, comprising:
- programming a memory cell to one of three possible data states by:
- applying a voltage pulse to the memory cell;
- determining whether the memory cell snaps back in response to the applied voltage pulse;
- determining a current data state of the memory cell based on the determination of whether the memory cell snaps back;
- and
- applying an additional voltage pulse to the memory cell based on the determination of the current data state of the memory cell.
An apparatus, comprising:
- a memory having a plurality of memory cells;
- and
- circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by:
- applying a first voltage pulse having a first polarity to the memory cell;
- determining whether the memory cell snaps back in response to the applied first voltage pulse;
- and
- applying a first additional voltage pulse to the memory cell upon determining the memory cell snaps back in response to the applied first voltage pulse, wherein the first additional pulse has a second polarity that is opposite the first polarity;
A method of operating memory, comprising:
- programming a memory cell to one of three possible data states by:
- applying a voltage pulse to the memory cell;
- determining whether the memory cell snaps back in response to the applied first voltage pulse;
- and
- applying a plurality of additional voltage pulses to the memory cell upon determining the memory cell does not snap back in response to the applied voltage pulse, wherein each of the plurality of additional voltage pulses has a same polarity as the voltage pulse.
An apparatus, comprising:
- a memory having a plurality of memory cells;
- and
- circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by:
- applying a first voltage pulse having a first polarity to the memory cell;
- determining whether the memory cell snaps back in response to the applied first voltage pulse;
- and
- applying a plurality of additional voltage pulses to the memory cell upon determining the memory cell snaps back in response to the applied first voltage pulse, wherein each of the plurality of additional voltage pulses has a second polarity that is opposite the first polarity.
Dependencies are inferred from the claim text.