Memory array structures and methods for determination of resistive characteristics of access lines

A memory array structure, comprising:

• a first block of memory cells including a first plurality of local access lines, wherein each local access line of the first plurality of local access lines is connected to control gates of a respective plurality of memory cells of the first block of memory cells;
• a second block of memory cells including a second plurality of local access lines, wherein each local access line of the second plurality of local access lines is connected to control gates of a respective plurality of memory cells of the second block of memory cells;
• a first current path between a particular local access line of the first plurality of local access lines and a particular local access line of the second plurality of local access lines;
• and
• a second current path between the particular local access line of the second plurality of local access lines and a different local access line of the first plurality of local access lines.

A memory, comprising:

• an array of memory cells including a plurality of blocks of memory cells, wherein each block of memory cells of the plurality of blocks of memory cells comprises a respective plurality of local access lines;
• and
• a controller, wherein the controller is configured to cause the memory to:
• connect each local access line of the respective plurality of local access lines of a selected block of memory cells of the plurality of blocks of memory cells to a respective global access line of a plurality of global access lines;
• connect a selected global access line of the plurality of global access lines to a reference current and to a first input of a comparator, wherein the comparator has a second input connected to receive a reference voltage,
• and wherein a current path is formed between a respective local access line of the respective plurality of local access lines of the selected block of memory cells for the selected global access line, and a local access line of the respective plurality of local access lines for an unselected block of memory cells of the plurality of blocks of memory cells;
• change a voltage level of the reference voltage until an output of the comparator makes a particular transition while the local access line of the respective plurality of local access lines for the unselected block of memory cells is connected to a voltage node;
• and
• determine a resistance value of the respective local access line of the respective plurality of local access lines of the selected block of memory for the selected global access line in response to a current level of the reference current and a voltage level of the reference voltage deemed to cause the particular transition of the output of the comparator.

A memory, comprising:

• an array of memory cells including a plurality of blocks of memory cells, wherein each block of memory cells of the plurality of blocks of memory cells comprises a respective plurality of local access lines;
• and
• a controller, wherein the controller is configured to cause the memory to:
• connect each local access line of the respective plurality of local access lines of a selected block of memory cells of the plurality of blocks of memory cells to a respective global access line of a plurality of global access lines;
• connect a selected global access line of the plurality of global access lines to a driver, wherein:
• a first current path is formed between a respective local access line of the respective plurality of local access lines of the selected block of memory cells for the selected global access line, and a local access line of the respective plurality of local access lines for an unselected block of memory cells of the plurality of blocks of memory cells;
• and
• a second current path is formed between the local access line of the respective plurality of local access lines of the unselected block of memory cells, and a different local access line of the respective plurality of local access lines of the selected block of memory cells;
• and
• determine a resistance value in response to a current level through the selected global access line and a voltage level of the selected global access line.

A memory, comprising:

• an array of memory cells including a plurality of blocks of memory cells, wherein each block of memory cells of the plurality of blocks of memory cells comprises a respective plurality of local access lines;
• and
• a controller, wherein the controller is configured to cause the memory to:
• connect each local access line of the respective plurality of local access lines of a selected block of memory cells of the plurality of blocks of memory cells to a respective global access line of a plurality of global access lines;
• connect a selected global access line of the plurality of global access lines to a reference current and to a first input of a comparator, wherein the comparator has a second input connected to receive a reference voltage, and wherein:
• a first current path is formed between a respective local access line of the respective plurality of local access lines of the selected block of memory cells for the selected global access line, and a local access line of the respective plurality of local access lines for an unselected block of memory cells of the plurality of blocks of memory cells;
• and
• a second current path is formed between the local access line of the respective plurality of local access lines of the unselected block of memory cells, and a different local access line of the respective plurality of local access lines of the selected block of memory cells for a different global access line of the plurality of global access lines;
• and
• connect the different global access line to a voltage node;
• change a voltage level of the reference voltage until an output of the comparator makes a particular transition;
• and
• determine a resistance value of the respective local access line of the respective plurality of local access lines of the selected block of memory for the selected global access line in response to a current level of the reference current and a voltage level of the reference voltage deemed to cause the particular transition of the output of the comparator.