Memory device, and electronic device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorGaram Kim
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array including M memory cells connected to one bit line and configured to distributively store N-bit data, where N is a natural number and M is a natural number of 2 or more and N or less, the M memory cells including a first memory cell and a second memory cell having different sensing margins, and a memory controller including a page buffer, the memory controller configured to distributively store the N-bit data in the M memory cells and to sequentially read data stored in the M memory cells to obtain the N-bit data, and an operation logic configured to execute an operation using the N-bit data, the memory controller configured to provide different reading voltages to the first memory cell and the second memory cell.
Claims25
A memory device comprising:
- a memory cell array including M memory cells connected to one bit line and configured to distributively store N-bit data, where N is a natural number and M is a natural number of 2 or more and N or less, the M memory cells including a first memory cell and a second memory cell, having different sensing margins;
- and
- a memory controller including a page buffer, the memory controller configured to distributively store the N-bit data in the M memory cells and to sequentially read data stored in the M memory cells to obtain the N-bit data, and including an operation logic configured to execute an operation using the N-bit data, the memory controller configured to provide different reading voltages to the first memory cell and the second memory cell.
(canceled)
14-15. (canceled)
A memory device comprising:
- a memory cell array including a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines;
- and
- a memory controller configured to select M memory cells continuously connected to one bit line, among the plurality of memory cells, where M is a natural number of 2 or more, and to divide N-bit data into M sets of bits, and to store the M sets of bits in the M memory cells, respectively, where N is a natural number more than or equal to M,
- wherein the M memory cells include a first memory cell for storing at least one upper bit of the N-bit data, and a second memory cell for storing at least one lower bit of the N-bit data, and
- the memory controller is configured to program the first memory cell, which has a first sensing margin, and to program the second memory cell, which has a second sensing margin less than the first sensing margin.
21-22. (canceled)
An electronic device comprising:
- a first memory device including:
- a memory cell array having a plurality of memory cells,
- a page buffer for reading N-bit data distributively stored in M memory cells connected to a bit line among the plurality of memory cells, based on the number of bit digits in the N-bit data, through the bit line, where M is a natural number of 2 or more, and
- an operation logic configured to process a neural network operation using the N-bit data;
- and
- a processor configured to receive result data of the neural network operation from the first memory device and to execute an application using the result data.
25-26. (canceled)
(canceled)
Dependencies are inferred from the claim text.