Write Assist for a Memory Device and Methods of Forming the Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao
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Abstract
A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
Claims20
A semiconductor memory device, comprising:
- an array of memory cells arranged in a column;
- and
- a write assist circuit within the column of the array of memory cells,
- the array of memory cells and the write assist circuit having a common semiconductor layout, wherein the common semiconductor layout includes a repeating pattern of gate regions and active regions every two rows in a vertical direction and every two columns in a horizontal direction.
A write assist circuit for a semiconductor memory device, comprising:
- a voltage bus configured to provide power to memory cells within the semiconductor memory device;
- a first pair of transistors coupled between a first voltage and the voltage bus;
- a second pair of transistors coupled between a second voltage and the voltage bus;
- the write assist circuit and the memory cells having a common semiconductor layout, wherein the common semiconductor layout includes a repeating pattern of gate regions and active regions every two rows in a vertical direction and every two columns in a horizontal direction.
A method of controlling a semiconductor memory device that includes an array of memory cells arranged in a column and a write assist circuit within the column, the method comprising:
- providing a core voltage to memory cells within the column;
- and
- wherein a common semiconductor layout includes a repeating pattern of gate regions and active regions every two rows in a vertical direction and every two columns in a horizontal direction.
Dependencies are inferred from the claim text.