Memory Device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
Life of this patent
Estimating the term…
Abstract
A memory device is provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.
Claims20
A memory device, comprising:
- a memory cell;
- a bit line connected to the memory cell;
- a negative voltage generator connected to the bit line, wherein the negative voltage generator is operative to provide a first write path for the bit line;
- and
- a control circuit connected to the negative voltage generator and the bit line, wherein the control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.
A memory device, comprising:
- a memory cell;
- a bit line connected to the memory cell;
- a first write path connected to the bit line, wherein the first write path comprises a negative voltage generator circuit operative to provide a negative voltage to the bit line;
- and
- a second write path connectable to the bit line, wherein the bit line is connected to the second write path in response to a write assist signal changing from a first value a second value.
A method for operating a memory device, the method comprising:
- receiving a write enable signal indicating a write operation in a memory device comprising a memory cell and a bit line connected to the memory cell;
- generating a write assist signal in response to the write enable signal;
- enabling a negative voltage generator in response to the write assist signal attaining a first value, the negative voltage generator providing a first write path to the bit line;
- and
- providing a second write path to the bit line in response to the write assist signal attaining a second value.
Dependencies are inferred from the claim text.