Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training

A method for restoring a memory context of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training, the method comprising:

• storing DRAM controller and DDR physical interface (PHY) settings into a non-volatile memory;
• powering down a DRAM controller and a DDR PHY;
• on system resume to restore the memory context after power down, restoring DRAM controller and DDR PHY settings from the non-volatile memory using a system basic input/output system (BIOS);
• resetting DRAMs;
• programing a self-refresh state machine memory operation (MOP) array to reinitialize a DRAM device state for a target power management state;
• and
• finalizing DRAM controller and DDR PHY settings for operation with the SOC.

A system for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training, the system comprising:

• a dynamic random-access memory (DRAM) controller and a DDR physical interface (PHY) with settings stored into a non-volatile memory;
• a plurality of DRAMs set into self-refresh mode,
• wherein the DRAM controller and the DDR PHY are powered down;
• on system resume for boot training, a system basic input/output system (BIOS) restoring DRAM controller and DDR PHY settings from the non-volatile memory;
• and
• a self-refresh state machine memory operation (MOP) array programmed to exit self-refresh mode and update any DRAM device state for a target power management state,
• wherein the DRAM controller and the DDR PHY settings are finalized for operation with the SOC.