Memory device including data input/output circuit
AssigneeSK hynix Inc.
InventorInsung KOH
Life of this patent
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Abstract
A memory device includes a plurality of data input/output (I/O) groups each including data I/O circuits, each data I/O circuit comprising a transistor having a predetermined threshold voltage according to a bulk voltage supplied to a bulk terminal thereof; a control circuit suitable for generating a control signal according to a data I/O mode; and a plurality of voltage supply circuits suitable for independently supplying bulk voltages to the plurality of data I/O groups, and changing, in response to the control signal, a level of a bulk voltage corresponding to data I/O groups unused in the data I/O mode, among the plurality of data I/O groups.
Claims20
A memory device comprising:
- a plurality of data input/output (I/O) groups each including data I/O circuits, each data I/O circuit comprising a transistor having a predetermined threshold voltage according to a bulk voltage supplied to a bulk terminal thereof;
- a control circuit suitable for generating a control signal according to a data I/O mode;
- and
- a plurality of voltage supply circuits suitable for independently supplying bulk voltages to the plurality of data I/O groups, and changing, in response to the control signal, a level of a bulk voltage corresponding to data I/O groups unused in the data I/O mode, among the plurality of data I/O groups.
A memory device comprising:
- a plurality of data input/output (I/O) groups each comprising a transistor coupled between a supply voltage terminal and a ground voltage terminal;
- and
- a plurality of voltage drivers suitable for driving a bulk voltage of the transistor included in a data I/O group unused in a data I/O mode, among the plurality of data I/O groups, at a boost voltage level higher than a supply voltage level or a back bias voltage level lower than a ground voltage level.
A memory device comprising:
- first to fourth data input/output (I/O) groups suitable for receiving and transmitting write data and read data;
- and
- first to fourth voltage supply circuits suitable for independently supplying bulk voltages of MOS transistors included in the first to fourth data I/O groups, and changing a bulk voltage of MOS transistors included in a data I/O group unused in a data I/O mode, among the first to fourth data I/O groups.
A memory device comprising:
- a plurality of data input/output (I/O) circuits suitable for receiving and transmitting write data and read data in parallel, each of the plurality of data I/O circuits including MOS transistors,
- wherein data I/O circuits used in a data I/O mode, among the plurality of data I/O circuits are supplied with a first bulk voltage for the MOS transistors, and
- wherein the other data I/O circuits unused in the data I/O mode, among the plurality of data I/O circuits are supplied with a second bulk voltage for the MOS transistors, which has a level different from the first bulk voltage to raise a threshold voltage of the MOS transistors.
Dependencies are inferred from the claim text.