Memory device and operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsYonghyuk CHOI, Sangwan NAM
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Abstract
A memory device includes a memory cell array including cell strings, respectively connected between string select lines and ground select lines, and wordlines connected to memory cells, a control logic to generate a first voltage provided to the string select lines, and a second voltage provided to the ground select lines, and to adjust voltage levels of the first and second voltages to control a channel boosting level of the cell strings, and a row decoder to provide a read voltage, a read pass voltage, and the first and second voltages to the memory cell array under control of the control logic. The control logic generates one of the first and second voltage as a pre-pulse voltage. The row decoder provides a third voltage to at least one of the wordlines.
Claims10
A memory device, comprising:
- a memory cell array including a plurality of cell strings each including a plurality of memory cells, respectively connected between a plurality of string select lines and a plurality of ground select lines, and a plurality of wordlines connected to the plurality of memory cells;
- a control logic configured to generate a first voltage that is provided to the plurality of string select lines, and a second voltage that is provided to the plurality of ground select lines, and to adjust each voltage level of the first voltage and the second voltage to control a channel boosting level of the plurality of cell strings;
- and
- a row decoder configured to provide a read voltage, a read pass voltage, the first voltage, and the second voltage to the memory cell array under control of the control logic, wherein:
- the control logic generates one of the first voltage and the second voltage as a pre-pulse voltage, and
- the row decoder provides a third voltage to at least one of the plurality of wordlines, the third voltage having a first level while the pre-pulse voltage has a level higher than or equal to a predetermined first threshold value, and having a second level higher than the first level while the pre-pulse voltage has a level lower than the first threshold value.
A memory device, comprising:
- a plurality of cell strings, each including a plurality of memory cells disposed at intersections of a plurality of wordlines and a plurality of bitlines, and connected between a plurality of string select lines and a plurality of ground select lines in series;
- and
- a control logic configured to select at least one of the plurality of cell strings to perform a read operation or a program verify operation, and to control a pre-pulse voltage such that the pre-pulse voltage is selectively input to a string select line or a ground select line, connected to an unselected cell string,
- wherein the pre-pulse voltage has a value that is greater than a predetermined threshold value during a period before a predetermined read voltage according to a threshold voltage distribution is input to a selected cell string, and has a value that is less than or equal to the predetermined threshold value during a period in which the predetermined read voltage is input.
A memory device, comprising:
- a memory cell array including a plurality of cell strings, including a plurality of memory cells, and a plurality of wordlines connected to the plurality of memory cells;
- a control logic configured such that a plurality of string select lines or a plurality of ground select lines, connected to the plurality of cell strings, are controlled to be pre-charged, and at least one of the plurality of wordlines is adjusted to control a potential level of each channel of the plurality of cell strings, to perform a read operation and a program verify operation;
- and
- a row decoder configured to input a read voltage or a read pass voltage to the plurality of wordlines to control the read operation or the program verify operation under control of the control logic,
- wherein the control logic selects at least one wordline, among wordlines connected to dummy memory cells among the plurality of memory cells, as a barrier line, and inputs a predetermined control voltage having a level that is lower than a level of the read pass voltage to control a potential level of the channel.
Dependencies are inferred from the claim text.