Semiconductor device with word line degradation monitor and associated methods and systems

A method, comprising:

• identifying a victim word line from a plurality of word lines of a memory bank, wherein the memory bank is included in a memory array of a memory device;
• generating a first signal based, at least in part, on executing a command at the victim word line, wherein the first signal corresponds to a voltage of the victim word line in response to executing the command;
• generating a reference signal based, at least in part, on executing the command at a word line of the plurality, wherein the reference signal corresponds to a voltage of the word line that is different from the victim word line;
• determining that a first transition included in the first signal lags behind a second transition included in the reference signal by more than a predetermined amount;
• and
• notifying a host device of the determination, the host device coupled with the memory device.

A system, comprising:

• a host device;
• and
• a memory device coupled with the host device, the memory device including:
• a memory array including a memory bank having a plurality of word lines;
• a reference component coupled with the memory array, and configured to generate a reference signal in response to a command directed to the memory array;
• and
• a comparison circuit coupled with the memory array and the reference component, the comparison circuit configured to:
• monitor the reference signal from the reference component;
• monitor a first signal from the memory bank, wherein the first signal is associated with the command executed at a word line of the plurality;
• detect a first transition in the first signal and a second transition in the reference signal;
• determine that the first transition occurs after the second transition;
• and
• notify the host device of the determination.